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3cc6243ddf
a SelectionDAG*. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59488 91177308-0d34-0410-b5e6-96231b3b80d8
519 lines
17 KiB
C++
519 lines
17 KiB
C++
//===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the ScheduleDAG class, which is a base class used by
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// scheduling implementation classes.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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ScheduleDAG::ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
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TII = TM.getInstrInfo();
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MF = BB->getParent();
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TRI = TM.getRegisterInfo();
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TLI = TM.getTargetLowering();
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ConstPool = MF->getConstantPool();
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}
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/// CheckForPhysRegDependency - Check if the dependency between def and use of
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/// a specified operand is a physical register dependency. If so, returns the
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/// register and the cost of copying the register.
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static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
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const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII,
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unsigned &PhysReg, int &Cost) {
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if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
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return;
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return;
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unsigned ResNo = User->getOperand(2).getResNo();
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if (Def->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
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if (ResNo >= II.getNumDefs() &&
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II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
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PhysReg = Reg;
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const TargetRegisterClass *RC =
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TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
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Cost = RC->getCopyCost();
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}
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}
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}
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SUnit *ScheduleDAG::Clone(SUnit *Old) {
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SUnit *SU = NewSUnit(Old->getNode());
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SU->OrigNode = Old->OrigNode;
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SU->Latency = Old->Latency;
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SU->isTwoAddress = Old->isTwoAddress;
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SU->isCommutable = Old->isCommutable;
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SU->hasPhysRegDefs = Old->hasPhysRegDefs;
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return SU;
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}
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/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
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/// This SUnit graph is similar to the SelectionDAG, but represents flagged
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/// together nodes with a single SUnit.
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void ScheduleDAG::BuildSchedUnits() {
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// For post-regalloc scheduling, build the SUnits from the MachineInstrs
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// in the MachineBasicBlock.
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if (!DAG) {
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BuildSchedUnitsFromMBB();
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return;
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}
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// Reserve entries in the vector for each of the SUnits we are creating. This
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// ensure that reallocation of the vector won't happen, so SUnit*'s won't get
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// invalidated.
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SUnits.reserve(DAG->allnodes_size());
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// During scheduling, the NodeId field of SDNode is used to map SDNodes
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// to their associated SUnits by holding SUnits table indices. A value
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// of -1 means the SDNode does not yet have an associated SUnit.
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI)
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NI->setNodeId(-1);
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI) {
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if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
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continue;
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// If this node has already been processed, stop now.
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if (NI->getNodeId() != -1) continue;
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SUnit *NodeSUnit = NewSUnit(NI);
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// See if anything is flagged to this node, if so, add them to flagged
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// nodes. Nodes can have at most one flag input and one flag output. Flags
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// are required the be the last operand and result of a node.
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// Scan up to find flagged preds.
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SDNode *N = NI;
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if (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
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do {
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N = N->getOperand(N->getNumOperands()-1).getNode();
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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} while (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
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}
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// Scan down to find any flagged succs.
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N = NI;
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while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
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SDValue FlagVal(N, N->getNumValues()-1);
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// There are either zero or one users of the Flag result.
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bool HasFlagUse = false;
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for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
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UI != E; ++UI)
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if (FlagVal.isOperandOf(*UI)) {
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HasFlagUse = true;
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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N = *UI;
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break;
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}
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if (!HasFlagUse) break;
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}
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// If there are flag operands involved, N is now the bottom-most node
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// of the sequence of nodes that are flagged together.
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// Update the SUnit.
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NodeSUnit->setNode(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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ComputeLatency(NodeSUnit);
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}
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// Pass 2: add the preds, succs, etc.
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
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SUnit *SU = &SUnits[su];
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SDNode *MainNode = SU->getNode();
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if (MainNode->isMachineOpcode()) {
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unsigned Opc = MainNode->getMachineOpcode();
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const TargetInstrDesc &TID = TII->get(Opc);
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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SU->isTwoAddress = true;
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break;
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}
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}
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if (TID.isCommutable())
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SU->isCommutable = true;
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}
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// Find all predecessors and successors of the group.
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for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
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if (N->isMachineOpcode() &&
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TII->get(N->getMachineOpcode()).getImplicitDefs() &&
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CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
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SU->hasPhysRegDefs = true;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDNode *OpN = N->getOperand(i).getNode();
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if (isPassiveNode(OpN)) continue; // Not scheduled.
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SUnit *OpSU = &SUnits[OpN->getNodeId()];
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assert(OpSU && "Node has no SUnit!");
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if (OpSU == SU) continue; // In the same group.
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MVT OpVT = N->getOperand(i).getValueType();
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assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
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bool isChain = OpVT == MVT::Other;
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unsigned PhysReg = 0;
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int Cost = 1;
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// Determine if this is a physical register dependency.
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CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
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SU->addPred(OpSU, isChain, false, PhysReg, Cost);
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}
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}
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}
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}
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void ScheduleDAG::BuildSchedUnitsFromMBB() {
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SUnits.clear();
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SUnits.reserve(BB->size());
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std::vector<SUnit *> PendingLoads;
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SUnit *Terminator = 0;
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SUnit *Chain = 0;
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SUnit *Defs[TargetRegisterInfo::FirstVirtualRegister] = {};
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std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister] = {};
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int Cost = 1; // FIXME
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for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin();
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MII != MIE; --MII) {
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MachineInstr *MI = prior(MII);
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SUnit *SU = NewSUnit(MI);
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for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
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std::vector<SUnit *> &UseList = Uses[Reg];
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SUnit *&Def = Defs[Reg];
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// Optionally add output and anti dependences
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if (Def && Def != SU)
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Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false,
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/*PhyReg=*/Reg, Cost);
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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SUnit *&Def = Defs[*Alias];
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if (Def && Def != SU)
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Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false,
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/*PhyReg=*/*Alias, Cost);
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}
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if (MO.isDef()) {
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// Add any data dependencies.
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false,
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/*PhysReg=*/Reg, Cost);
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false,
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/*PhysReg=*/*Alias, Cost);
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}
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UseList.clear();
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Def = SU;
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} else {
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UseList.push_back(SU);
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}
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}
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bool False = false;
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bool True = true;
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if (!MI->isSafeToMove(TII, False)) {
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if (Chain)
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Chain->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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PendingLoads[k]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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PendingLoads.clear();
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Chain = SU;
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} else if (!MI->isSafeToMove(TII, True)) {
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if (Chain)
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Chain->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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PendingLoads.push_back(SU);
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}
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if (Terminator && SU->Succs.empty())
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Terminator->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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if (MI->getDesc().isTerminator())
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Terminator = SU;
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}
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}
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void ScheduleDAG::ComputeLatency(SUnit *SU) {
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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if (InstrItins.isEmpty()) {
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// No latency information.
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SU->Latency = 1;
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return;
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}
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SU->Latency = 0;
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for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
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if (N->isMachineOpcode()) {
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unsigned SchedClass = TII->get(N->getMachineOpcode()).getSchedClass();
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const InstrStage *S = InstrItins.begin(SchedClass);
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const InstrStage *E = InstrItins.end(SchedClass);
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for (; S != E; ++S)
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SU->Latency += S->Cycles;
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}
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}
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}
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/// CalculateDepths - compute depths using algorithms for the longest
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/// paths in the DAG
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void ScheduleDAG::CalculateDepths() {
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unsigned DAGSize = SUnits.size();
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std::vector<SUnit*> WorkList;
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WorkList.reserve(DAGSize);
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// Initialize the data structures
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for (unsigned i = 0, e = DAGSize; i != e; ++i) {
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SUnit *SU = &SUnits[i];
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unsigned Degree = SU->Preds.size();
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// Temporarily use the Depth field as scratch space for the degree count.
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SU->Depth = Degree;
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// Is it a node without dependencies?
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if (Degree == 0) {
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assert(SU->Preds.empty() && "SUnit should have no predecessors");
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// Collect leaf nodes
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WorkList.push_back(SU);
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}
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}
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// Process nodes in the topological order
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while (!WorkList.empty()) {
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SUnit *SU = WorkList.back();
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WorkList.pop_back();
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unsigned SUDepth = 0;
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// Use dynamic programming:
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// When current node is being processed, all of its dependencies
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// are already processed.
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// So, just iterate over all predecessors and take the longest path
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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unsigned PredDepth = I->Dep->Depth;
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if (PredDepth+1 > SUDepth) {
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SUDepth = PredDepth + 1;
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}
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}
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SU->Depth = SUDepth;
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// Update degrees of all nodes depending on current SUnit
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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SUnit *SU = I->Dep;
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if (!--SU->Depth)
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// If all dependencies of the node are processed already,
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// then the longest path for the node can be computed now
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WorkList.push_back(SU);
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}
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}
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}
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/// CalculateHeights - compute heights using algorithms for the longest
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/// paths in the DAG
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void ScheduleDAG::CalculateHeights() {
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unsigned DAGSize = SUnits.size();
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std::vector<SUnit*> WorkList;
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WorkList.reserve(DAGSize);
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// Initialize the data structures
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for (unsigned i = 0, e = DAGSize; i != e; ++i) {
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SUnit *SU = &SUnits[i];
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unsigned Degree = SU->Succs.size();
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// Temporarily use the Height field as scratch space for the degree count.
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SU->Height = Degree;
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// Is it a node without dependencies?
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if (Degree == 0) {
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assert(SU->Succs.empty() && "Something wrong");
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assert(WorkList.empty() && "Should be empty");
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// Collect leaf nodes
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WorkList.push_back(SU);
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}
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}
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// Process nodes in the topological order
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while (!WorkList.empty()) {
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SUnit *SU = WorkList.back();
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WorkList.pop_back();
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unsigned SUHeight = 0;
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// Use dynamic programming:
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// When current node is being processed, all of its dependencies
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// are already processed.
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// So, just iterate over all successors and take the longest path
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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unsigned SuccHeight = I->Dep->Height;
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if (SuccHeight+1 > SUHeight) {
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SUHeight = SuccHeight + 1;
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}
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}
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SU->Height = SUHeight;
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// Update degrees of all nodes depending on current SUnit
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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SUnit *SU = I->Dep;
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if (!--SU->Height)
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// If all dependencies of the node are processed already,
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// then the longest path for the node can be computed now
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WorkList.push_back(SU);
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}
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}
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}
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands (which do
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/// not go into the resulting MachineInstr).
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unsigned ScheduleDAG::CountResults(SDNode *Node) {
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Flag)
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--N;
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if (N && Node->getValueType(N - 1) == MVT::Other)
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--N; // Skip over chain result.
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return N;
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}
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by special operands that describe memory references, then an
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/// optional chain operand, then an optional flag operand. Compute the number
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/// of actual operands that will go into the resulting MachineInstr.
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unsigned ScheduleDAG::CountOperands(SDNode *Node) {
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unsigned N = ComputeMemOperandsEnd(Node);
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while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
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--N; // Ignore MEMOPERAND nodes
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return N;
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}
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/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
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/// operand
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unsigned ScheduleDAG::ComputeMemOperandsEnd(SDNode *Node) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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return N;
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}
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/// dump - dump the schedule.
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void ScheduleDAG::dumpSchedule() const {
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for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
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if (SUnit *SU = Sequence[i])
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SU->dump(this);
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else
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cerr << "**** NOOP ****\n";
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}
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}
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/// Run - perform scheduling.
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///
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void ScheduleDAG::Run() {
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Schedule();
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DOUT << "*** Final schedule ***\n";
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DEBUG(dumpSchedule());
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DOUT << "\n";
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}
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/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
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/// a group of nodes flagged together.
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void SUnit::dump(const ScheduleDAG *G) const {
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cerr << "SU(" << NodeNum << "): ";
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if (getNode())
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getNode()->dump(G->DAG);
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else
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cerr << "CROSS RC COPY ";
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cerr << "\n";
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SmallVector<SDNode *, 4> FlaggedNodes;
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for (SDNode *N = getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
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FlaggedNodes.push_back(N);
|
|
while (!FlaggedNodes.empty()) {
|
|
cerr << " ";
|
|
FlaggedNodes.back()->dump(G->DAG);
|
|
cerr << "\n";
|
|
FlaggedNodes.pop_back();
|
|
}
|
|
}
|
|
|
|
void SUnit::dumpAll(const ScheduleDAG *G) const {
|
|
dump(G);
|
|
|
|
cerr << " # preds left : " << NumPredsLeft << "\n";
|
|
cerr << " # succs left : " << NumSuccsLeft << "\n";
|
|
cerr << " Latency : " << Latency << "\n";
|
|
cerr << " Depth : " << Depth << "\n";
|
|
cerr << " Height : " << Height << "\n";
|
|
|
|
if (Preds.size() != 0) {
|
|
cerr << " Predecessors:\n";
|
|
for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl)
|
|
cerr << " ch #";
|
|
else
|
|
cerr << " val #";
|
|
cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
|
|
if (I->isSpecial)
|
|
cerr << " *";
|
|
cerr << "\n";
|
|
}
|
|
}
|
|
if (Succs.size() != 0) {
|
|
cerr << " Successors:\n";
|
|
for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl)
|
|
cerr << " ch #";
|
|
else
|
|
cerr << " val #";
|
|
cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
|
|
if (I->isSpecial)
|
|
cerr << " *";
|
|
cerr << "\n";
|
|
}
|
|
}
|
|
cerr << "\n";
|
|
}
|