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https://github.com/c64scene-ar/llvm-6502.git
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d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
903 B
LLVM
40 lines
903 B
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
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;define ptx_device i32 @t1(i32 %x, i32 %y) {
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; %z = mul i32 %x, %y
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; ret i32 %z
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;}
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;define ptx_device i32 @t2(i32 %x) {
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; %z = mul i32 %x, 1
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; ret i32 %z
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;}
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define ptx_device float @t1_f32(float %x, float %y) {
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; CHECK: mul.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
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; CHECK-NEXT: ret;
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%z = fmul float %x, %y
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ret float %z
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}
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define ptx_device double @t1_f64(double %x, double %y) {
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; CHECK: mul.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}
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; CHECK-NEXT: ret;
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%z = fmul double %x, %y
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ret double %z
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}
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define ptx_device float @t2_f32(float %x) {
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; CHECK: mul.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, 0F40A00000;
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; CHECK-NEXT: ret;
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%z = fmul float %x, 5.0
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ret float %z
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}
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define ptx_device double @t2_f64(double %x) {
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; CHECK: mul.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, 0D4014000000000000;
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; CHECK-NEXT: ret;
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%z = fmul double %x, 5.0
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ret double %z
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}
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