Evan Cheng 8b944d39b3 Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code. ... e.g. orl $65536, 8(%rax) => orb $1, 10(%rax) Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8		2009-05-28 00:35:15 +00:00
..
Alpha
ARM	Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and	2009-05-19 10:02:36 +00:00
CBackend
CellSPU
CPP	Fix code emission for conditional branches.	2009-05-04 19:10:38 +00:00
Generic	Add a new codegen pass that normalizes dwarf exception handling	2009-05-22 20:36:31 +00:00
IA64
Mips	This looks like it passes now.	2009-05-27 17:43:21 +00:00
MSP430	Fix for PR4235: to build a floating-point value from integer parts,	2009-05-20 06:02:09 +00:00
PowerPC	Help DejaGnu avoid pipe-jam by producing less output from certain test cases.	2009-05-16 00:34:42 +00:00
SPARC
X86	Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.	2009-05-28 00:35:15 +00:00
XCore	Fix for PR4235: to build a floating-point value from integer parts,	2009-05-20 06:02:09 +00:00