Tom Stellard 898b9f020d TableGen: Generate a function for getting operand indices based on their defined names ... This patch modifies TableGen to generate a function in ${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used to look up indices for operands based on their names. In order to activate this feature for an instruction, you must set the UseNamedOperandTable bit. For example, if you have an instruction like: def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>; You can look up the operand indices using the new function, like this: Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2 The operand names are case sensitive, so $dst and $DST are considered different operands. This change is useful for R600 which has instructions with a large number of operands, many of which model single bit instruction configuration values. These configuration bits are common across most instructions, but may have a different operand index depending on the instruction type. It is useful to have a convenient way to look up the operand indices, so these bits can be generically set on any instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-25 21:22:09 +00:00
..
AsmMatcherEmitter.cpp	Handle tied sub-operands in AsmMatcherEmitter	2013-04-27 18:48:23 +00:00
AsmWriterEmitter.cpp
AsmWriterInst.cpp
AsmWriterInst.h
CallingConvEmitter.cpp
CMakeLists.txt
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp
CodeGenDAGPatterns.h
CodeGenInstruction.cpp
CodeGenInstruction.h
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp	Make SubRegIndex size mandatory, following r183020.	2013-05-31 23:45:26 +00:00
CodeGenRegisters.h	Make SubRegIndex size mandatory, following r183020.	2013-05-31 23:45:26 +00:00
CodeGenSchedule.cpp	Support BufferSize on ProcResGroup for unified MOp schedulers.	2013-06-15 04:50:06 +00:00
CodeGenSchedule.h	Support BufferSize on ProcResGroup for unified MOp schedulers.	2013-06-15 04:50:06 +00:00
CodeGenTarget.cpp
CodeGenTarget.h
CTagsEmitter.cpp
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp
FastISelEmitter.cpp	Recognize ValueType operands in source patterns for fast-isel.	2013-05-22 20:45:11 +00:00
FixedLenDecoderEmitter.cpp
InstrInfoEmitter.cpp	TableGen: Generate a function for getting operand indices based on their defined names	2013-06-25 21:22:09 +00:00
IntrinsicEmitter.cpp
LLVMBuild.txt
Makefile
OptParserEmitter.cpp
PseudoLoweringEmitter.cpp
RegisterInfoEmitter.cpp	Remove unimplemented definition. Found using [-Wunused-member-function].	2013-06-06 17:52:45 +00:00
SequenceToOffsetTable.h
SetTheory.cpp
SetTheory.h
StringToOffsetTable.h
SubtargetEmitter.cpp	Support BufferSize on ProcResGroup for unified MOp schedulers.	2013-06-15 04:50:06 +00:00
TableGen.cpp
TableGenBackends.h
tdtags
TGValueTypes.cpp
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp	Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.	2013-06-18 17:08:10 +00:00
X86RecognizableInstr.h