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https://github.com/c64scene-ar/llvm-6502.git
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573630a020
This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222583 91177308-0d34-0410-b5e6-96231b3b80d8
284 lines
12 KiB
LLVM
284 lines
12 KiB
LLVM
; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
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; Test that doing a shift of a pointer with a constant add will be
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; folded into the constant offset addressing mode even if the add has
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; multiple uses. This is relevant to accessing 2 separate, adjacent
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; LDS globals.
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declare i32 @llvm.r600.read.tidig.x() #1
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@lds0 = addrspace(3) global [512 x float] undef, align 4
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@lds1 = addrspace(3) global [512 x float] undef, align 4
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; Make sure the (add tid, 2) << 2 gets folded into the ds's offset as (tid << 2) + 8
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; SI-LABEL: {{^}}load_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8 [M0]
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; SI: s_endpgm
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define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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store float %val0, float addrspace(1)* %out
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ret void
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}
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; Make sure once the first use is folded into the addressing mode, the
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; remaining add use goes through the normal shl + add constant fold.
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; SI-LABEL: {{^}}load_shl_base_lds_1:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8 [M0]
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; SI: v_add_i32_e32 [[ADDUSE:v[0-9]+]], 8, v{{[0-9]+}}
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; SI-DAG: buffer_store_dword [[RESULT]]
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; SI-DAG: buffer_store_dword [[ADDUSE]]
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; SI: s_endpgm
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define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%shl_add_use = shl i32 %idx.0, 2
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store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4
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store float %val0, float addrspace(1)* %out
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ret void
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}
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@maxlds = addrspace(3) global [65536 x i8] undef, align 4
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; SI-LABEL: {{^}}load_shl_base_lds_max_offset
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; SI: ds_read_u8 v{{[0-9]+}}, v{{[0-9]+}} offset:65535
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; SI: s_endpgm
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define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 65535
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%arrayidx0 = getelementptr inbounds [65536 x i8] addrspace(3)* @maxlds, i32 0, i32 %idx.0
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%val0 = load i8 addrspace(3)* %arrayidx0
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store i32 %idx.0, i32 addrspace(1)* %add_use
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store i8 %val0, i8 addrspace(1)* %out
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ret void
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}
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; The two globals are placed adjacent in memory, so the same base
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; pointer can be used with an offset into the second one.
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; SI-LABEL: {{^}}load_shl_base_lds_2:
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; SI: s_mov_b32 m0, -1
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; SI-NEXT: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 [M0]
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; SI: s_endpgm
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define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 64
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0
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%val1 = load float addrspace(3)* %arrayidx1, align 4
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%sum = fadd float %val0, %val1
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store float %sum, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}store_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8 [M0]
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; SI: s_endpgm
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define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
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store float 1.0, float addrspace(3)* %arrayidx0, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; --------------------------------------------------------------------------------
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; Atomics.
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@lds2 = addrspace(3) global [512 x i32] undef, align 4
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; define void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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; %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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; %idx.0 = add nsw i32 %tid.x, 2
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; %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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; %val = load atomic i32 addrspace(3)* %arrayidx0 seq_cst, align 4
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; store i32 %val, i32 addrspace(1)* %out, align 4
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; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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; ret void
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; }
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; SI-LABEL: {{^}}atomic_cmpxchg_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_cmpst_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use, i32 %swap) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%pair = cmpxchg i32 addrspace(3)* %arrayidx0, i32 7, i32 %swap seq_cst monotonic
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%result = extractvalue { i32, i1 } %pair, 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_swap_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_wrxchg_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw xchg i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_add_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw add i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_sub_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_sub_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw sub i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_and_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_and_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw and i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_or_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_or_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw or i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_xor_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_xor_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw xor i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; define void @atomic_nand_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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; %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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; %idx.0 = add nsw i32 %tid.x, 2
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; %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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; %val = atomicrmw nand i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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; store i32 %val, i32 addrspace(1)* %out, align 4
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; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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; ret void
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; }
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; SI-LABEL: {{^}}atomic_min_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_min_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw min i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_max_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw max i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_umin_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_min_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw umin i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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; SI-LABEL: {{^}}atomic_umax_shl_base_lds_0:
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; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: ds_max_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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; SI: s_endpgm
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define void @atomic_umax_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
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%val = atomicrmw umax i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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