mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
448 lines
13 KiB
LLVM
448 lines
13 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
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; CHECK-LABEL: @test1
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; CHECK: vmovd %xmm0, %eax ## encoding: [0x62
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; CHECK: ret
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define i32 @test1(float %x) {
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%res = bitcast float %x to i32
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ret i32 %res
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}
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; CHECK-LABEL: @test2
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; CHECK: vmovd %edi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test2(i32 %x) {
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%res = insertelement <4 x i32>undef, i32 %x, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test3
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; CHECK: vmovq %rdi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <2 x i64> @test3(i64 %x) {
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%res = insertelement <2 x i64>undef, i64 %x, i32 0
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ret <2 x i64>%res
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}
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; CHECK-LABEL: @test4
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; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test4(i32* %x) {
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%y = load i32, i32* %x
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%res = insertelement <4 x i32>undef, i32 %y, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test5
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; CHECK: vmovss %xmm0, (%rdi) ## encoding: [0x62
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; CHECK: ret
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define void @test5(float %x, float* %y) {
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store float %x, float* %y, align 4
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ret void
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}
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; CHECK-LABEL: @test6
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; CHECK: vmovsd %xmm0, (%rdi) ## encoding: [0x62
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; CHECK: ret
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define void @test6(double %x, double* %y) {
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store double %x, double* %y, align 8
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ret void
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}
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; CHECK-LABEL: @test7
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; CHECK: vmovss (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define float @test7(i32* %x) {
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%y = load i32, i32* %x
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%res = bitcast i32 %y to float
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ret float %res
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}
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; CHECK-LABEL: @test8
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; CHECK: vmovd %xmm0, %eax ## encoding: [0x62
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; CHECK: ret
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define i32 @test8(<4 x i32> %x) {
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%res = extractelement <4 x i32> %x, i32 0
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ret i32 %res
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}
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; CHECK-LABEL: @test9
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; CHECK: vmovq %xmm0, %rax ## encoding: [0x62
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; CHECK: ret
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define i64 @test9(<2 x i64> %x) {
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%res = extractelement <2 x i64> %x, i32 0
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ret i64 %res
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}
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; CHECK-LABEL: @test10
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; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test10(i32* %x) {
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%y = load i32, i32* %x, align 4
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%res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test11
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; CHECK: vmovss (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x float> @test11(float* %x) {
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%y = load float, float* %x, align 4
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%res = insertelement <4 x float>zeroinitializer, float %y, i32 0
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ret <4 x float>%res
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}
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; CHECK-LABEL: @test12
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; CHECK: vmovsd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <2 x double> @test12(double* %x) {
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%y = load double, double* %x, align 8
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%res = insertelement <2 x double>zeroinitializer, double %y, i32 0
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ret <2 x double>%res
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}
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; CHECK-LABEL: @test13
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; CHECK: vmovq %rdi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <2 x i64> @test13(i64 %x) {
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%res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0
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ret <2 x i64>%res
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}
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; CHECK-LABEL: @test14
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; CHECK: vmovd %edi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test14(i32 %x) {
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%res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test15
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; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test15(i32* %x) {
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%y = load i32, i32* %x, align 4
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%res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: test16
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; CHECK: vmovdqu32
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; CHECK: ret
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define <16 x i32> @test16(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%res = load <16 x i32>, <16 x i32>* %vaddr, align 1
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test17
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test17(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%res = load <16 x i32>, <16 x i32>* %vaddr, align 64
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test18
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; CHECK: vmovdqa64
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; CHECK: ret
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define void @test18(i8 * %addr, <8 x i64> %data) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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store <8 x i64>%data, <8 x i64>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test19
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; CHECK: vmovdqu32
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; CHECK: ret
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define void @test19(i8 * %addr, <16 x i32> %data) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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store <16 x i32>%data, <16 x i32>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test20
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; CHECK: vmovdqa32
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; CHECK: ret
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define void @test20(i8 * %addr, <16 x i32> %data) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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store <16 x i32>%data, <16 x i32>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test21
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; CHECK: vmovdqa64
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; CHECK: ret
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define <8 x i64> @test21(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%res = load <8 x i64>, <8 x i64>* %vaddr, align 64
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test22
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; CHECK: vmovdqu64
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; CHECK: ret
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define void @test22(i8 * %addr, <8 x i64> %data) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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store <8 x i64>%data, <8 x i64>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test23
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; CHECK: vmovdqu64
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; CHECK: ret
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define <8 x i64> @test23(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%res = load <8 x i64>, <8 x i64>* %vaddr, align 1
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test24
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; CHECK: vmovapd
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; CHECK: ret
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define void @test24(i8 * %addr, <8 x double> %data) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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store <8 x double>%data, <8 x double>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test25
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; CHECK: vmovapd
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; CHECK: ret
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define <8 x double> @test25(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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%res = load <8 x double>, <8 x double>* %vaddr, align 64
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ret <8 x double>%res
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}
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; CHECK-LABEL: test26
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; CHECK: vmovaps
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; CHECK: ret
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define void @test26(i8 * %addr, <16 x float> %data) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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store <16 x float>%data, <16 x float>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test27
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; CHECK: vmovaps
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; CHECK: ret
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define <16 x float> @test27(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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%res = load <16 x float>, <16 x float>* %vaddr, align 64
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ret <16 x float>%res
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}
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; CHECK-LABEL: test28
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; CHECK: vmovupd
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; CHECK: ret
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define void @test28(i8 * %addr, <8 x double> %data) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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store <8 x double>%data, <8 x double>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test29
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; CHECK: vmovupd
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; CHECK: ret
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define <8 x double> @test29(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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%res = load <8 x double>, <8 x double>* %vaddr, align 1
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ret <8 x double>%res
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}
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; CHECK-LABEL: test30
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; CHECK: vmovups
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; CHECK: ret
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define void @test30(i8 * %addr, <16 x float> %data) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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store <16 x float>%data, <16 x float>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test31
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; CHECK: vmovups
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; CHECK: ret
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define <16 x float> @test31(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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%res = load <16 x float>, <16 x float>* %vaddr, align 1
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ret <16 x float>%res
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}
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; CHECK-LABEL: test32
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; CHECK: vmovdqa32{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x i32> @test32(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>, <16 x i32>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test33
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; CHECK: vmovdqu32{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x i32> @test33(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>, <16 x i32>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test34
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; CHECK: vmovdqa32{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x i32> @test34(i8 * %addr, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>, <16 x i32>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test35
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; CHECK: vmovdqu32{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x i32> @test35(i8 * %addr, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>, <16 x i32>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test36
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; CHECK: vmovdqa64{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x i64> @test36(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>, <8 x i64>* %vaddr, align 64
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test37
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; CHECK: vmovdqu64{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x i64> @test37(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>, <8 x i64>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test38
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; CHECK: vmovdqa64{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x i64> @test38(i8 * %addr, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>, <8 x i64>* %vaddr, align 64
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test39
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; CHECK: vmovdqu64{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x i64> @test39(i8 * %addr, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>, <8 x i64>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test40
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; CHECK: vmovaps{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x float> @test40(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>, <16 x float>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
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ret <16 x float>%res
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}
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; CHECK-LABEL: test41
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; CHECK: vmovups{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x float> @test41(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>, <16 x float>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
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ret <16 x float>%res
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}
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; CHECK-LABEL: test42
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; CHECK: vmovaps{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x float> @test42(i8 * %addr, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>, <16 x float>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
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ret <16 x float>%res
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}
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; CHECK-LABEL: test43
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; CHECK: vmovups{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x float> @test43(i8 * %addr, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>, <16 x float>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
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ret <16 x float>%res
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}
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; CHECK-LABEL: test44
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; CHECK: vmovapd{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x double> @test44(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
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%mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <8 x double>*
|
|
%r = load <8 x double>, <8 x double>* %vaddr, align 64
|
|
%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
|
|
ret <8 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test45
|
|
; CHECK: vmovupd{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <8 x double> @test45(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
|
|
%mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <8 x double>*
|
|
%r = load <8 x double>, <8 x double>* %vaddr, align 1
|
|
%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
|
|
ret <8 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test46
|
|
; CHECK: vmovapd{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <8 x double> @test46(i8 * %addr, <8 x double> %mask1) {
|
|
%mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <8 x double>*
|
|
%r = load <8 x double>, <8 x double>* %vaddr, align 64
|
|
%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
|
|
ret <8 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test47
|
|
; CHECK: vmovupd{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <8 x double> @test47(i8 * %addr, <8 x double> %mask1) {
|
|
%mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <8 x double>*
|
|
%r = load <8 x double>, <8 x double>* %vaddr, align 1
|
|
%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
|
|
ret <8 x double>%res
|
|
}
|