mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
b1ff87ec86
Previously the patterns didn't have high enough priority and we would only use the GR32 form if the only the upper 32 or 56 bits were zero. Fixes PR23100. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234075 91177308-0d34-0410-b5e6-96231b3b80d8
393 lines
8.8 KiB
LLVM
393 lines
8.8 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+bmi,+bmi2 | FileCheck %s
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declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone
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declare i16 @llvm.cttz.i16(i16, i1) nounwind readnone
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
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define i8 @t1(i8 %x) nounwind {
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%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
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ret i8 %tmp
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; CHECK-LABEL: t1:
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; CHECK: tzcntl
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}
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define i16 @t2(i16 %x) nounwind {
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%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 false )
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ret i16 %tmp
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; CHECK-LABEL: t2:
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; CHECK: tzcntw
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}
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define i32 @t3(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 false )
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ret i32 %tmp
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; CHECK-LABEL: t3:
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; CHECK: tzcntl
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}
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define i32 @tzcnt32_load(i32* %x) nounwind {
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%x1 = load i32, i32* %x
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%tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false )
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ret i32 %tmp
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; CHECK-LABEL: tzcnt32_load:
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; CHECK: tzcntl ({{.*}})
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}
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define i64 @t4(i64 %x) nounwind {
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%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false )
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ret i64 %tmp
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; CHECK-LABEL: t4:
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; CHECK: tzcntq
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}
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define i8 @t5(i8 %x) nounwind {
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%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
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ret i8 %tmp
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; CHECK-LABEL: t5:
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; CHECK: tzcntl
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}
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define i16 @t6(i16 %x) nounwind {
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%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true )
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ret i16 %tmp
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; CHECK-LABEL: t6:
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; CHECK: tzcntw
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}
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define i32 @t7(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
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ret i32 %tmp
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; CHECK-LABEL: t7:
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; CHECK: tzcntl
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}
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define i64 @t8(i64 %x) nounwind {
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%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true )
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ret i64 %tmp
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; CHECK-LABEL: t8:
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; CHECK: tzcntq
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}
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define i32 @andn32(i32 %x, i32 %y) nounwind readnone {
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%tmp1 = xor i32 %x, -1
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%tmp2 = and i32 %y, %tmp1
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ret i32 %tmp2
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; CHECK-LABEL: andn32:
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; CHECK: andnl
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}
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define i32 @andn32_load(i32 %x, i32* %y) nounwind readnone {
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%y1 = load i32, i32* %y
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%tmp1 = xor i32 %x, -1
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%tmp2 = and i32 %y1, %tmp1
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ret i32 %tmp2
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; CHECK-LABEL: andn32_load:
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; CHECK: andnl ({{.*}})
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}
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define i64 @andn64(i64 %x, i64 %y) nounwind readnone {
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%tmp1 = xor i64 %x, -1
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%tmp2 = and i64 %tmp1, %y
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ret i64 %tmp2
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; CHECK-LABEL: andn64:
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; CHECK: andnq
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}
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define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK-LABEL: bextr32:
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; CHECK: bextrl
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}
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define i32 @bextr32_load(i32* %x, i32 %y) nounwind readnone {
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%x1 = load i32, i32* %x
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%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y)
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ret i32 %tmp
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; CHECK-LABEL: bextr32_load:
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; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
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}
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declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
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define i32 @bextr32b(i32 %x) nounwind uwtable readnone ssp {
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%1 = lshr i32 %x, 4
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%2 = and i32 %1, 4095
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ret i32 %2
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; CHECK-LABEL: bextr32b:
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; CHECK: bextrl
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}
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define i32 @bextr32b_load(i32* %x) nounwind uwtable readnone ssp {
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%1 = load i32, i32* %x
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%2 = lshr i32 %1, 4
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%3 = and i32 %2, 4095
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ret i32 %3
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; CHECK-LABEL: bextr32b_load:
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; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
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}
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define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK-LABEL: bextr64:
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; CHECK: bextrq
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}
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
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define i64 @bextr64b(i64 %x) nounwind uwtable readnone ssp {
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%1 = lshr i64 %x, 4
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%2 = and i64 %1, 4095
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ret i64 %2
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; CHECK-LABEL: bextr64b:
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; CHECK: bextrq
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}
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define i64 @bextr64b_load(i64* %x) {
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%1 = load i64, i64* %x, align 8
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%2 = lshr i64 %1, 4
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%3 = and i64 %2, 4095
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ret i64 %3
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; CHECK-LABEL: bextr64b_load:
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; CHECK: bextrq {{.*}}, ({{.*}}), {{.*}}
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}
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define i32 @non_bextr32(i32 %x) {
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entry:
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%shr = lshr i32 %x, 2
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%and = and i32 %shr, 111
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ret i32 %and
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; CHECK-LABEL: non_bextr32:
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; CHECK: shrl $2
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; CHECK: andl $111
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}
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define i64 @non_bextr64(i64 %x) {
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entry:
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%shr = lshr i64 %x, 2
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%and = and i64 %shr, 8589934590
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ret i64 %and
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; CHECK-LABEL: non_bextr64:
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; CHECK: shrq $2
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; CHECK: movabsq $8589934590
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; CHECK: andq
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}
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define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK-LABEL: bzhi32:
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; CHECK: bzhil
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}
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define i32 @bzhi32_load(i32* %x, i32 %y) nounwind readnone {
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%x1 = load i32, i32* %x
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%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y)
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ret i32 %tmp
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; CHECK-LABEL: bzhi32_load:
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; CHECK: bzhil {{.*}}, ({{.*}}), {{.*}}
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}
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declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone
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define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK-LABEL: bzhi64:
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; CHECK: bzhiq
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}
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declare i64 @llvm.x86.bmi.bzhi.64(i64, i64) nounwind readnone
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define i32 @bzhi32b(i32 %x, i8 zeroext %index) #0 {
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entry:
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%conv = zext i8 %index to i32
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%shl = shl i32 1, %conv
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%sub = add nsw i32 %shl, -1
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%and = and i32 %sub, %x
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ret i32 %and
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; CHECK-LABEL: bzhi32b:
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; CHECK: bzhil
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}
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define i32 @bzhi32b_load(i32* %w, i8 zeroext %index) #0 {
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entry:
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%x = load i32, i32* %w
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%conv = zext i8 %index to i32
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%shl = shl i32 1, %conv
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%sub = add nsw i32 %shl, -1
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%and = and i32 %sub, %x
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ret i32 %and
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; CHECK-LABEL: bzhi32b_load:
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; CHECK: bzhil {{.*}}, ({{.*}}), {{.*}}
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}
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define i32 @bzhi32c(i32 %x, i8 zeroext %index) #0 {
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entry:
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%conv = zext i8 %index to i32
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%shl = shl i32 1, %conv
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%sub = add nsw i32 %shl, -1
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%and = and i32 %x, %sub
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ret i32 %and
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; CHECK-LABEL: bzhi32c:
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; CHECK: bzhil
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}
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define i64 @bzhi64b(i64 %x, i8 zeroext %index) #0 {
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entry:
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%conv = zext i8 %index to i64
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%shl = shl i64 1, %conv
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%sub = add nsw i64 %shl, -1
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%and = and i64 %x, %sub
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ret i64 %and
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; CHECK-LABEL: bzhi64b:
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; CHECK: bzhiq
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}
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define i64 @bzhi64_constant_mask(i64 %x) #0 {
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entry:
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%and = and i64 %x, 4611686018427387903
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ret i64 %and
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; CHECK-LABEL: bzhi64_constant_mask:
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; CHECK: movb $62, %al
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; CHECK: bzhiq %rax, %r[[ARG1:di|cx]], %rax
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}
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define i64 @bzhi64_small_constant_mask(i64 %x) #0 {
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entry:
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%and = and i64 %x, 2147483647
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ret i64 %and
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; CHECK-LABEL: bzhi64_small_constant_mask:
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; CHECK: andl $2147483647, %e[[ARG1]]
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}
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define i32 @blsi32(i32 %x) nounwind readnone {
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%tmp = sub i32 0, %x
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%tmp2 = and i32 %x, %tmp
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ret i32 %tmp2
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; CHECK-LABEL: blsi32:
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; CHECK: blsil
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}
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define i32 @blsi32_load(i32* %x) nounwind readnone {
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%x1 = load i32, i32* %x
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%tmp = sub i32 0, %x1
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%tmp2 = and i32 %x1, %tmp
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ret i32 %tmp2
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; CHECK-LABEL: blsi32_load:
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; CHECK: blsil ({{.*}})
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}
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define i64 @blsi64(i64 %x) nounwind readnone {
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%tmp = sub i64 0, %x
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%tmp2 = and i64 %tmp, %x
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ret i64 %tmp2
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; CHECK-LABEL: blsi64:
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; CHECK: blsiq
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}
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define i32 @blsmsk32(i32 %x) nounwind readnone {
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%tmp = sub i32 %x, 1
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%tmp2 = xor i32 %x, %tmp
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ret i32 %tmp2
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; CHECK-LABEL: blsmsk32:
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; CHECK: blsmskl
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}
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define i32 @blsmsk32_load(i32* %x) nounwind readnone {
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%x1 = load i32, i32* %x
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%tmp = sub i32 %x1, 1
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%tmp2 = xor i32 %x1, %tmp
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ret i32 %tmp2
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; CHECK-LABEL: blsmsk32_load:
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; CHECK: blsmskl ({{.*}})
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}
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define i64 @blsmsk64(i64 %x) nounwind readnone {
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%tmp = sub i64 %x, 1
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%tmp2 = xor i64 %tmp, %x
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ret i64 %tmp2
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; CHECK-LABEL: blsmsk64:
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; CHECK: blsmskq
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}
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define i32 @blsr32(i32 %x) nounwind readnone {
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%tmp = sub i32 %x, 1
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%tmp2 = and i32 %x, %tmp
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ret i32 %tmp2
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; CHECK-LABEL: blsr32:
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; CHECK: blsrl
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}
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define i32 @blsr32_load(i32* %x) nounwind readnone {
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%x1 = load i32, i32* %x
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%tmp = sub i32 %x1, 1
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%tmp2 = and i32 %x1, %tmp
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ret i32 %tmp2
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; CHECK-LABEL: blsr32_load:
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; CHECK: blsrl ({{.*}})
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}
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define i64 @blsr64(i64 %x) nounwind readnone {
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%tmp = sub i64 %x, 1
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%tmp2 = and i64 %tmp, %x
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ret i64 %tmp2
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; CHECK-LABEL: blsr64:
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; CHECK: blsrq
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}
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define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK-LABEL: pdep32:
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; CHECK: pdepl
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}
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define i32 @pdep32_load(i32 %x, i32* %y) nounwind readnone {
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%y1 = load i32, i32* %y
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%tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1)
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ret i32 %tmp
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; CHECK-LABEL: pdep32_load:
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; CHECK: pdepl ({{.*}})
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}
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declare i32 @llvm.x86.bmi.pdep.32(i32, i32) nounwind readnone
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define i64 @pdep64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK-LABEL: pdep64:
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; CHECK: pdepq
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}
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declare i64 @llvm.x86.bmi.pdep.64(i64, i64) nounwind readnone
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define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK-LABEL: pext32:
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; CHECK: pextl
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}
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define i32 @pext32_load(i32 %x, i32* %y) nounwind readnone {
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%y1 = load i32, i32* %y
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%tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1)
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ret i32 %tmp
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; CHECK-LABEL: pext32_load:
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; CHECK: pextl ({{.*}})
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}
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declare i32 @llvm.x86.bmi.pext.32(i32, i32) nounwind readnone
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define i64 @pext64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK-LABEL: pext64:
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; CHECK: pextq
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}
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declare i64 @llvm.x86.bmi.pext.64(i64, i64) nounwind readnone
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