mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
c4af4638df
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
267 lines
6.2 KiB
LLVM
267 lines
6.2 KiB
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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; Test #<const>
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; var 2.1 - 0x00ab00ab
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define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
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;CHECK: t2_const_var2_1_ok_1:
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;CHECK: add.w r0, r0, #11206827
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%ret = add i32 %lhs, 11206827 ; 0x00ab00ab
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
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;CHECK: t2_const_var2_1_ok_2:
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;CHECK: add.w r0, r0, #11206656
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;CHECK: adds r0, #187
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%ret = add i32 %lhs, 11206843 ; 0x00ab00bb
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
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;CHECK: t2_const_var2_1_ok_3:
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;CHECK: add.w r0, r0, #11206827
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;CHECK: add.w r0, r0, #16777216
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%ret = add i32 %lhs, 27984043 ; 0x01ab00ab
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
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;CHECK: t2_const_var2_1_ok_4:
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;CHECK: add.w r0, r0, #16777472
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;CHECK: add.w r0, r0, #11206827
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%ret = add i32 %lhs, 27984299 ; 0x01ab01ab
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
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;CHECK: t2_const_var2_1_fail_1:
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;CHECK: movw r1, #43777
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;CHECK: movt r1, #427
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;CHECK: add r0, r1
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%ret = add i32 %lhs, 28027649 ; 0x01abab01
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ret i32 %ret
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}
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; var 2.2 - 0xab00ab00
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define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
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;CHECK: t2_const_var2_2_ok_1:
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;CHECK: add.w r0, r0, #-1426019584
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%ret = add i32 %lhs, 2868947712 ; 0xab00ab00
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
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;CHECK: t2_const_var2_2_ok_2:
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;CHECK: add.w r0, r0, #2868903936
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;CHECK: add.w r0, r0, #47616
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%ret = add i32 %lhs, 2868951552 ; 0xab00ba00
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
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;CHECK: t2_const_var2_2_ok_3:
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;CHECK: add.w r0, r0, #2868947712
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;CHECK: adds r0, #16
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%ret = add i32 %lhs, 2868947728 ; 0xab00ab10
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
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;CHECK: t2_const_var2_2_ok_4:
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;CHECK: add.w r0, r0, #2868947712
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;CHECK: add.w r0, r0, #1048592
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%ret = add i32 %lhs, 2869996304 ; 0xab10ab10
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
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;CHECK: t2_const_var2_2_fail_1:
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;CHECK: movw r1, #43792
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;CHECK: movt r1, #4267
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;CHECK: add r0, r1
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%ret = add i32 %lhs, 279685904 ; 0x10abab10
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ret i32 %ret
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}
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; var 2.3 - 0xabababab
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define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
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;CHECK: t2_const_var2_3_ok_1:
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;CHECK: add.w r0, r0, #-1414812757
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%ret = add i32 %lhs, 2880154539 ; 0xabababab
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ret i32 %ret
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}
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define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
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;CHECK: t2_const_var2_3_fail_1:
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;CHECK: movw r1, #43962
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;CHECK: movt r1, #43947
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;CHECK: add r0, r1
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%ret = add i32 %lhs, 2880154554 ; 0xabababba
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ret i32 %ret
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}
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define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
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;CHECK: t2_const_var2_3_fail_2:
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;CHECK: movw r1, #47787
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;CHECK: movt r1, #43947
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;CHECK: add r0, r1
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%ret = add i32 %lhs, 2880158379 ; 0xababbaab
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ret i32 %ret
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}
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define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
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;CHECK: t2_const_var2_3_fail_3:
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;CHECK: movw r1, #43947
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;CHECK: movt r1, #43962
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;CHECK: add r0, r1
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%ret = add i32 %lhs, 2881137579 ; 0xabbaabab
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ret i32 %ret
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}
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define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
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;CHECK: t2_const_var2_3_fail_4:
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;CHECK: movw r1, #43947
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;CHECK: movt r1, #47787
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;CHECK: add r0, r1
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%ret = add i32 %lhs, 3131812779 ; 0xbaababab
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ret i32 %ret
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}
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; var 3 - 0x0F000000
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define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
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;CHECK: t2_const_var3_1_ok_1:
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;CHECK: add.w r0, r0, #251658240
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%ret = add i32 %lhs, 251658240 ; 0x0F000000
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ret i32 %ret
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}
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define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
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;CHECK: t2_const_var3_2_ok_1:
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;CHECK: add.w r0, r0, #3948544
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%ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
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ret i32 %ret
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}
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define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
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;CHECK: t2_const_var3_2_ok_2:
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;CHECK: add.w r0, r0, #2097152
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;CHECK: add.w r0, r0, #1843200
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%ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
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ret i32 %ret
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}
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define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
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;CHECK: t2_const_var3_3_ok_1:
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;CHECK: add.w r0, r0, #258
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%ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
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ret i32 %ret
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}
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define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
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;CHECK: t2_const_var3_4_ok_1:
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;CHECK: add.w r0, r0, #-268435456
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%ret = add i32 %lhs, 4026531840 ; 0xF0000000
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ret i32 %ret
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}
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define i32 @t2MOVTi16_ok_1(i32 %a) {
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; CHECK: t2MOVTi16_ok_1:
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; CHECK: movt r0, #1234
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%1 = and i32 %a, 65535
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%2 = shl i32 1234, 16
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%3 = or i32 %1, %2
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ret i32 %3
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}
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define i32 @t2MOVTi16_test_1(i32 %a) {
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; CHECK: t2MOVTi16_test_1:
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; CHECK: movt r0, #1234
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%1 = shl i32 255, 8
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%2 = shl i32 1234, 8
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%3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
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%4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4
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%5 = and i32 %a, %3
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%6 = or i32 %4, %5
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ret i32 %6
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}
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define i32 @t2MOVTi16_test_2(i32 %a) {
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; CHECK: t2MOVTi16_test_2:
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; CHECK: movt r0, #1234
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%1 = shl i32 255, 8
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%2 = shl i32 1234, 8
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%3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
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%4 = shl i32 %2, 6
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%5 = and i32 %a, %3
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%6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
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%7 = or i32 %5, %6
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ret i32 %7
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}
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define i32 @t2MOVTi16_test_3(i32 %a) {
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; CHECK: t2MOVTi16_test_3:
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; CHECK: movt r0, #1234
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%1 = shl i32 255, 8
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%2 = shl i32 1234, 8
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%3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
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%4 = shl i32 %2, 6
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%5 = and i32 %a, %3
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%6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
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%7 = lshr i32 %6, 6
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%8 = shl i32 %7, 6
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%9 = or i32 %5, %8
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ret i32 %8
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}
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; 171 = 0x000000ab
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define i32 @f1(i32 %a) {
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; CHECK: f1:
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; CHECK: movs r0, #171
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%tmp = add i32 0, 171
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ret i32 %tmp
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}
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; 1179666 = 0x00120012
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define i32 @f2(i32 %a) {
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; CHECK: f2:
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; CHECK: mov.w r0, #1179666
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%tmp = add i32 0, 1179666
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ret i32 %tmp
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}
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; 872428544 = 0x34003400
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define i32 @f3(i32 %a) {
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; CHECK: f3:
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; CHECK: mov.w r0, #872428544
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%tmp = add i32 0, 872428544
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ret i32 %tmp
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}
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; 1448498774 = 0x56565656
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define i32 @f4(i32 %a) {
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; CHECK: f4:
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; CHECK: mov.w r0, #1448498774
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%tmp = add i32 0, 1448498774
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ret i32 %tmp
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}
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; 66846720 = 0x03fc0000
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define i32 @f5(i32 %a) {
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; CHECK: f5:
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; CHECK: mov.w r0, #66846720
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%tmp = add i32 0, 66846720
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ret i32 %tmp
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}
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define i32 @f6(i32 %a) {
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;CHECK: f6
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;CHECK: movw r0, #65535
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%tmp = add i32 0, 65535
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ret i32 %tmp
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}
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