Bill Wendling 8c3befd76e This test is failing. Revert for now. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73404 91177308-0d34-0410-b5e6-96231b3b80d8		2009-06-15 19:10:56 +00:00
..
Alpha
ARM	Part 1.	2009-06-15 08:28:29 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
CPP
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec	2009-06-07 01:07:55 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
X86	This test is failing. Revert for now.	2009-06-15 19:10:56 +00:00
XCore	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00