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https://github.com/c64scene-ar/llvm-6502.git
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5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
762 B
LLVM
26 lines
762 B
LLVM
; This test should cause the TargetMaterializeAlloca to be invoked
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; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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%struct.S1Ty = type { i64 }
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%struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty }
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define void @takeS1(%struct.S1Ty* %V) nounwind {
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entry:
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%V.addr = alloca %struct.S1Ty*, align 8
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store %struct.S1Ty* %V, %struct.S1Ty** %V.addr, align 8
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ret void
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}
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define void @main() nounwind {
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entry:
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; CHECK: main
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; CHECK: mov x29, sp
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; CHECK: mov x[[REG:[0-9]+]], sp
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; CHECK-NEXT: orr x[[REG1:[0-9]+]], xzr, #0x8
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; CHECK-NEXT: add x0, x[[REG]], x[[REG1]]
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%E = alloca %struct.S2Ty, align 4
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%B = getelementptr inbounds %struct.S2Ty* %E, i32 0, i32 1
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call void @takeS1(%struct.S1Ty* %B)
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ret void
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}
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