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https://github.com/c64scene-ar/llvm-6502.git
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9c4127a6a5
As v1i1 is illegal, the type legalizer tries to scalarize such node. But if the type operands of SETCC is legal, the scalarization algorithm will cause an assertion failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201381 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.5 KiB
LLVM
69 lines
2.5 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
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; is illegal in AArch64 backend, the legalizer tries to scalarize this node.
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; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
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; Currently the type legalizer will have an assertion failure as it assumes all
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; operands of SETCC have been legalized.
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; FIXME: If the algorithm of type scalarization is improved and can legaize
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; "v1i1 SETCC" correctly, these test cases are not needed.
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define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {
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; CHECK-LABEL: test_sext_extr_cmp_0:
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; CHECK: cmge d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = icmp sge <1 x i64> %v1, %v2
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%2 = extractelement <1 x i1> %1, i32 0
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%vget_lane = sext i1 %2 to i64
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ret i64 %vget_lane
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}
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define i64 @test_sext_extr_cmp_1(<1 x double> %v1, <1 x double> %v2) {
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; CHECK-LABEL: test_sext_extr_cmp_1:
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; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fcmp oeq <1 x double> %v1, %v2
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%2 = extractelement <1 x i1> %1, i32 0
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%vget_lane = sext i1 %2 to i64
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ret i64 %vget_lane
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}
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define <1 x i64> @test_select_v1i1_0(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
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; CHECK-LABEL: test_select_v1i1_0:
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; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bsl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%1 = icmp eq <1 x i64> %v1, %v2
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%res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
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ret <1 x i64> %res
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}
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define <1 x i64> @test_select_v1i1_1(<1 x double> %v1, <1 x double> %v2, <1 x i64> %v3) {
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; CHECK-LABEL: test_select_v1i1_1:
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; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bsl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%1 = fcmp oeq <1 x double> %v1, %v2
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%res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
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ret <1 x i64> %res
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}
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define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x double> %v3) {
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; CHECK-LABEL: test_select_v1i1_2:
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; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bsl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%1 = icmp eq <1 x i64> %v1, %v2
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%res = select <1 x i1> %1, <1 x double> zeroinitializer, <1 x double> %v3
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ret <1 x double> %res
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}
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define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) {
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; CHECK-LABEL: test_br_extr_cmp:
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; CHECK: cmp x{{[0-9]+}}, x{{[0-9]+}}
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%1 = icmp eq <1 x i64> %v1, %v2
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%2 = extractelement <1 x i1> %1, i32 0
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br i1 %2, label %if.end, label %if.then
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if.then:
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ret i32 0;
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if.end:
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ret i32 1;
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}
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