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104de4390b
(a) Improve the extract element code: there's no need to do gymnastics with
rotates into the preferred slot if a shuffle will do the same thing.
(b) Rename a couple of SPUISD pseudo-instructions for readability and better
semantic correspondence.
(c) Fix i64 sign/any/zero extension lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59965 91177308-0d34-0410-b5e6-96231b3b80d8
149 lines
6.7 KiB
C++
149 lines
6.7 KiB
C++
//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Cell SPU uses to lower LLVM code into
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// a selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPU_ISELLOWERING_H
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#define SPU_ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "SPU.h"
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namespace llvm {
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namespace SPUISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Pseudo instructions:
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RET_FLAG, ///< Return with flag, matched by bi instruction
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Hi, ///< High address component (upper 16)
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Lo, ///< Low address component (lower 16)
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PCRelAddr, ///< Program counter relative address
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AFormAddr, ///< A-form address (local store)
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IndirectAddr, ///< D-Form "imm($r)" and X-form "$r($r)"
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LDRESULT, ///< Load result (value, chain)
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CALL, ///< CALL instruction
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SHUFB, ///< Vector shuffle (permute)
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SHUFFLE_MASK, ///< Shuffle mask
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CNTB, ///< Count leading ones in bytes
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PROMOTE_SCALAR, ///< Promote scalar->vector
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VEC2PREFSLOT, ///< Extract element 0
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VEC2PREFSLOT_CHAINED, ///< Extract element 0, with chain
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EXTRACT_I1_ZEXT, ///< Extract element 0 as i1, zero extend
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EXTRACT_I1_SEXT, ///< Extract element 0 as i1, sign extend
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EXTRACT_I8_ZEXT, ///< Extract element 0 as i8, zero extend
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EXTRACT_I8_SEXT, ///< Extract element 0 as i8, sign extend
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MPY, ///< 16-bit Multiply (low parts of a 32-bit)
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MPYU, ///< Multiply Unsigned
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MPYH, ///< Multiply High
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MPYHH, ///< Multiply High-High
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SHLQUAD_L_BITS, ///< Rotate quad left, by bits
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SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes
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VEC_SHL, ///< Vector shift left
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VEC_SRL, ///< Vector shift right (logical)
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VEC_SRA, ///< Vector shift right (arithmetic)
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VEC_ROTL, ///< Vector rotate left
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VEC_ROTR, ///< Vector rotate right
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ROTQUAD_RZ_BYTES, ///< Rotate quad right, by bytes, zero fill
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ROTQUAD_RZ_BITS, ///< Rotate quad right, by bits, zero fill
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ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
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ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain
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ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count
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SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
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SELB, ///< Select bits -> (b & mask) | (a & ~mask)
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ADD_EXTENDED, ///< Add extended, with carry
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CARRY_GENERATE, ///< Carry generate for ADD_EXTENDED
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SUB_EXTENDED, ///< Subtract extended, with borrow
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BORROW_GENERATE, ///< Borrow generate for SUB_EXTENDED
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FPInterp, ///< Floating point interpolate
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FPRecipEst, ///< Floating point reciprocal estimate
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SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits
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LAST_SPUISD ///< Last user-defined instruction
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};
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}
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/// Predicates that are used for node matching:
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namespace SPU {
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SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
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MVT ValueType);
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SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
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MVT ValueType);
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SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
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MVT ValueType);
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SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
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MVT ValueType);
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SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
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MVT ValueType);
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SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
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SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
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}
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class SPUTargetMachine; // forward dec'l.
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class SPUTargetLowering :
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public TargetLowering
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{
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int ReturnAddrIndex; // FrameIndex for return slot.
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SPUTargetMachine &SPUTM;
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public:
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SPUTargetLowering(SPUTargetMachine &TM);
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/// getTargetNodeName() - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - Return the ValueType for ISD::SETCC
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virtual MVT getSetCCResultType(const SDValue &) const;
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//! Custom lowering hooks
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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//! Provide custom lowering hooks for nodes with illegal result types.
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SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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const APInt &Mask,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode.
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virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
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virtual bool isLegalAddressImmediate(GlobalValue *) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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};
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}
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#endif
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