llvm-6502/lib/CodeGen/SelectionDAG
Cameron Zwarich 8ca814c4e0 Merge information about the number of zero, one, and sign bits of live-out
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:25 +00:00
..
CMakeLists.txt
DAGCombiner.cpp
FastISel.cpp
FunctionLoweringInfo.cpp Merge information about the number of zero, one, and sign bits of live-out 2011-02-24 10:00:25 +00:00
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
SDNodeDbgValue.h
SDNodeOrdering.h
SelectionDAG.cpp Add a getNumSignBits() method to APInt. 2011-02-24 10:00:20 +00:00
SelectionDAGBuilder.cpp
SelectionDAGBuilder.h
SelectionDAGISel.cpp Merge information about the number of zero, one, and sign bits of live-out 2011-02-24 10:00:25 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp
TargetSelectionDAGInfo.cpp