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https://github.com/c64scene-ar/llvm-6502.git
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8ca814c4e0
registers at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes <rdar://problem/8760114>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.3 KiB
LLVM
36 lines
1.3 KiB
LLVM
; RUN: llc < %s -march=x86-64 | FileCheck %s
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%"class.std::bitset" = type { [8 x i8] }
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define zeroext i1 @_Z3fooPjmS_mRSt6bitsetILm32EE(i32* nocapture %a, i64 %asize, i32* nocapture %b, i64 %bsize, %"class.std::bitset"* %bits) nounwind readonly ssp noredzone {
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entry:
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%tmp.i.i.i.i = bitcast %"class.std::bitset"* %bits to i64*
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%conv = zext i32 %0 to i64
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%cmp = icmp eq i64 %conv, %bsize
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br i1 %cmp, label %return, label %for.body
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for.body: ; preds = %for.cond
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%arrayidx = getelementptr inbounds i32* %b, i64 %conv
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%tmp5 = load i32* %arrayidx, align 4
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%conv6 = zext i32 %tmp5 to i64
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%rem.i.i.i.i = and i64 %conv6, 63
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%tmp3.i = load i64* %tmp.i.i.i.i, align 8
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%shl.i.i = shl i64 1, %rem.i.i.i.i
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%and.i = and i64 %shl.i.i, %tmp3.i
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%cmp.i = icmp eq i64 %and.i, 0
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br i1 %cmp.i, label %for.inc, label %return
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for.inc: ; preds = %for.body
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%inc = add i32 %0, 1
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br label %for.cond
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return: ; preds = %for.body, %for.cond
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; CHECK-NOT: and
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%retval.0 = phi i1 [ true, %for.body ], [ false, %for.cond ]
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ret i1 %retval.0
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}
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