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8cc3474f72
llvm-6502/test/CodeGen
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Hal Finkel 8cc3474f72 Add readcyclecounter lowering on PPC64. 
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 14:10:46 +00:00
..
ARM Add stack spill / reload instructions for DTriple and DQuad register classes, which 2012-08-04 13:16:12 +00:00
CellSPU Refactor and check "onlyReadsMemory" before optimizing builtins. 2012-08-03 23:29:17 +00:00
CPP test commit 2012-07-18 17:53:05 +00:00
Generic
Hexagon Refactor and check "onlyReadsMemory" before optimizing builtins. 2012-08-03 23:29:17 +00:00
MBlaze
Mips 1. Redo mips16 instructions to avoid multiple opcodes for same instruction. 2012-08-03 22:57:02 +00:00
MSP430
NVPTX
PowerPC Add readcyclecounter lowering on PPC64. 2012-08-04 14:10:46 +00:00
SPARC
Thumb
Thumb2 [arm-fast-isel] Add support for vararg function calls. 2012-07-19 09:49:00 +00:00
X86 Refactor and check "onlyReadsMemory" before optimizing builtins. 2012-08-03 23:29:17 +00:00
XCore