mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
159 lines
5.1 KiB
LLVM
159 lines
5.1 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test2:
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; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1) * %in
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%b = load <2 x i32> addrspace(1) * %b_ptr
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%result = and <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test4:
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1) * %in
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%b = load <4 x i32> addrspace(1) * %b_ptr
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%result = and <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_i32:
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; SI: s_and_b32
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define void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_constant_i32:
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687
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define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) {
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%and = and i32 %a, 1234567
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i32:
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; SI: v_and_b32
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define void @v_and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) {
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%a = load i32 addrspace(1)* %aptr, align 4
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%b = load i32 addrspace(1)* %bptr, align 4
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_constant_i32:
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; SI: v_and_b32
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define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
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%a = load i32 addrspace(1)* %aptr, align 4
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%and = and i32 %a, 1234567
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_i64:
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; SI: s_and_b64
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define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%and = and i64 %a, %b
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Should use SGPRs
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; FUNC-LABEL: {{^}}s_and_i1:
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; SI: v_and_b32
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define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
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%and = and i1 %a, %b
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store i1 %and, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_constant_i64:
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; SI: s_and_b64
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define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
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%and = and i64 %a, 281474976710655
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i64:
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; SI: v_and_b32
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; SI: v_and_b32
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define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
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%a = load i64 addrspace(1)* %aptr, align 8
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%b = load i64 addrspace(1)* %bptr, align 8
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%and = and i64 %a, %b
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i64_br:
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; SI: v_and_b32
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; SI: v_and_b32
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define void @v_and_i64_br(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i32 %cond) {
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entry:
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%a = load i64 addrspace(1)* %aptr, align 8
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%b = load i64 addrspace(1)* %bptr, align 8
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%and = and i64 %a, %b
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br label %endif
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endif:
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%tmp1 = phi i64 [%and, %if], [0, %entry]
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store i64 %tmp1, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_constant_i64:
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; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 1234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Replace and 0 with mov 0
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; FUNC-LABEL: {{^}}v_and_inline_imm_i64:
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; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}}
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; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
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define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 64
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_i64:
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64
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define void @s_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 64
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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