mirror of
https://github.com/c64scene-ar/llvm-6502.git
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5d78275493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83587 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.6 KiB
LLVM
86 lines
2.6 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovns16:
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;CHECK: vqmovn.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovns32:
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;CHECK: vqmovn.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovns64:
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;CHECK: vqmovn.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovnu16:
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;CHECK: vqmovn.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovnu32:
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;CHECK: vqmovn.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovnu64:
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;CHECK: vqmovn.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
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;CHECK: vqmovuns16:
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;CHECK: vqmovun.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
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;CHECK: vqmovuns32:
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;CHECK: vqmovun.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
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;CHECK: vqmovuns64:
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;CHECK: vqmovun.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
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