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When a BL/BLX references a symbol in the same translation unit that is out of range, use an external relocation. The linker will use this to generate a branch island rather than a direct reference, allowing the relocation to resolve correctly. rdar://12359919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
497 lines
19 KiB
C++
497 lines
19 KiB
C++
//===-- ARMMachObjectWriter.cpp - ARM Mach Object Writer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "MCTargetDesc/ARMFixupKinds.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCAsmLayout.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCMachOSymbolFlags.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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using namespace llvm::object;
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namespace {
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class ARMMachObjectWriter : public MCMachObjectTargetWriter {
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void RecordARMScatteredRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFragment *Fragment,
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const MCFixup &Fixup,
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MCValue Target,
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unsigned Log2Size,
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uint64_t &FixedValue);
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void RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFragment *Fragment,
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const MCFixup &Fixup, MCValue Target,
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uint64_t &FixedValue);
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bool requiresExternRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm,
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const MCFragment &Fragment,
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unsigned RelocType, const MCSymbolData *SD,
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uint64_t FixedValue);
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public:
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ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
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uint32_t CPUSubtype)
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: MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
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/*UseAggressiveSymbolFolding=*/true) {}
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void RecordRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFragment *Fragment, const MCFixup &Fixup,
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MCValue Target, uint64_t &FixedValue);
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};
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}
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static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
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unsigned &Log2Size) {
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RelocType = unsigned(macho::RIT_Vanilla);
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Log2Size = ~0U;
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switch (Kind) {
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default:
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return false;
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case FK_Data_1:
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Log2Size = llvm::Log2_32(1);
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return true;
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case FK_Data_2:
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Log2Size = llvm::Log2_32(2);
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return true;
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case FK_Data_4:
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Log2Size = llvm::Log2_32(4);
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return true;
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case FK_Data_8:
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Log2Size = llvm::Log2_32(8);
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return true;
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// Handle 24-bit branch kinds.
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case ARM::fixup_arm_ldst_pcrel_12:
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case ARM::fixup_arm_pcrel_10:
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case ARM::fixup_arm_adr_pcrel_12:
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case ARM::fixup_arm_condbranch:
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case ARM::fixup_arm_uncondbranch:
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case ARM::fixup_arm_uncondbl:
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case ARM::fixup_arm_condbl:
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case ARM::fixup_arm_blx:
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RelocType = unsigned(macho::RIT_ARM_Branch24Bit);
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// Report as 'long', even though that is not quite accurate.
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Log2Size = llvm::Log2_32(4);
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return true;
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// Handle Thumb branches.
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case ARM::fixup_arm_thumb_br:
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RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
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Log2Size = llvm::Log2_32(2);
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return true;
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case ARM::fixup_t2_uncondbranch:
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case ARM::fixup_arm_thumb_bl:
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case ARM::fixup_arm_thumb_blx:
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RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
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Log2Size = llvm::Log2_32(4);
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return true;
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// For movw/movt r_type relocations they always have a pair following them and
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// the r_length bits are used differently. The encoding of the r_length is as
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// follows:
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// low bit of r_length:
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// 0 - :lower16: for movw instructions
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// 1 - :upper16: for movt instructions
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// high bit of r_length:
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// 0 - arm instructions
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// 1 - thumb instructions
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movt_hi16_pcrel:
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RelocType = unsigned(macho::RIT_ARM_Half);
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Log2Size = 1;
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return true;
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case ARM::fixup_t2_movt_hi16:
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case ARM::fixup_t2_movt_hi16_pcrel:
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RelocType = unsigned(macho::RIT_ARM_Half);
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Log2Size = 3;
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return true;
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case ARM::fixup_arm_movw_lo16:
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case ARM::fixup_arm_movw_lo16_pcrel:
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RelocType = unsigned(macho::RIT_ARM_Half);
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Log2Size = 0;
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return true;
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case ARM::fixup_t2_movw_lo16:
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case ARM::fixup_t2_movw_lo16_pcrel:
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RelocType = unsigned(macho::RIT_ARM_Half);
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Log2Size = 2;
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return true;
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}
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}
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void ARMMachObjectWriter::
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RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFragment *Fragment,
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const MCFixup &Fixup,
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MCValue Target,
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uint64_t &FixedValue) {
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uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
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unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
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unsigned Type = macho::RIT_ARM_Half;
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// See <reloc.h>.
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const MCSymbol *A = &Target.getSymA()->getSymbol();
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MCSymbolData *A_SD = &Asm.getSymbolData(*A);
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if (!A_SD->getFragment())
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Asm.getContext().FatalError(Fixup.getLoc(),
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"symbol '" + A->getName() +
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"' can not be undefined in a subtraction expression");
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uint32_t Value = Writer->getSymbolAddress(A_SD, Layout);
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uint32_t Value2 = 0;
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uint64_t SecAddr =
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Writer->getSectionAddress(A_SD->getFragment()->getParent());
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FixedValue += SecAddr;
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if (const MCSymbolRefExpr *B = Target.getSymB()) {
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MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
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if (!B_SD->getFragment())
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Asm.getContext().FatalError(Fixup.getLoc(),
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"symbol '" + B->getSymbol().getName() +
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"' can not be undefined in a subtraction expression");
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// Select the appropriate difference relocation type.
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Type = macho::RIT_ARM_HalfDifference;
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Value2 = Writer->getSymbolAddress(B_SD, Layout);
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FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent());
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}
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// Relocations are written out in reverse order, so the PAIR comes first.
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// ARM_RELOC_HALF and ARM_RELOC_HALF_SECTDIFF abuse the r_length field:
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//
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// For these two r_type relocations they always have a pair following them and
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// the r_length bits are used differently. The encoding of the r_length is as
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// follows:
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// low bit of r_length:
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// 0 - :lower16: for movw instructions
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// 1 - :upper16: for movt instructions
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// high bit of r_length:
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// 0 - arm instructions
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// 1 - thumb instructions
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// the other half of the relocated expression is in the following pair
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// relocation entry in the low 16 bits of r_address field.
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unsigned ThumbBit = 0;
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unsigned MovtBit = 0;
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switch ((unsigned)Fixup.getKind()) {
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default: break;
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movt_hi16_pcrel:
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MovtBit = 1;
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// The thumb bit shouldn't be set in the 'other-half' bit of the
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// relocation, but it will be set in FixedValue if the base symbol
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// is a thumb function. Clear it out here.
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if (A_SD->getFlags() & SF_ThumbFunc)
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FixedValue &= 0xfffffffe;
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break;
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case ARM::fixup_t2_movt_hi16:
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case ARM::fixup_t2_movt_hi16_pcrel:
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if (A_SD->getFlags() & SF_ThumbFunc)
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FixedValue &= 0xfffffffe;
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MovtBit = 1;
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// Fallthrough
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case ARM::fixup_t2_movw_lo16:
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case ARM::fixup_t2_movw_lo16_pcrel:
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ThumbBit = 1;
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break;
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}
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if (Type == macho::RIT_ARM_HalfDifference) {
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uint32_t OtherHalf = MovtBit
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? (FixedValue & 0xffff) : ((FixedValue & 0xffff0000) >> 16);
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macho::RelocationEntry MRE;
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MRE.Word0 = ((OtherHalf << 0) |
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(macho::RIT_Pair << 24) |
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(MovtBit << 28) |
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(ThumbBit << 29) |
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(IsPCRel << 30) |
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macho::RF_Scattered);
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MRE.Word1 = Value2;
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Writer->addRelocation(Fragment->getParent(), MRE);
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}
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macho::RelocationEntry MRE;
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MRE.Word0 = ((FixupOffset << 0) |
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(Type << 24) |
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(MovtBit << 28) |
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(ThumbBit << 29) |
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(IsPCRel << 30) |
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macho::RF_Scattered);
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MRE.Word1 = Value;
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Writer->addRelocation(Fragment->getParent(), MRE);
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}
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void ARMMachObjectWriter::RecordARMScatteredRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFragment *Fragment,
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const MCFixup &Fixup,
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MCValue Target,
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unsigned Log2Size,
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uint64_t &FixedValue) {
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uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
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unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
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unsigned Type = macho::RIT_Vanilla;
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// See <reloc.h>.
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const MCSymbol *A = &Target.getSymA()->getSymbol();
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MCSymbolData *A_SD = &Asm.getSymbolData(*A);
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if (!A_SD->getFragment())
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Asm.getContext().FatalError(Fixup.getLoc(),
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"symbol '" + A->getName() +
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"' can not be undefined in a subtraction expression");
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uint32_t Value = Writer->getSymbolAddress(A_SD, Layout);
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uint64_t SecAddr = Writer->getSectionAddress(A_SD->getFragment()->getParent());
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FixedValue += SecAddr;
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uint32_t Value2 = 0;
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if (const MCSymbolRefExpr *B = Target.getSymB()) {
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MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
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if (!B_SD->getFragment())
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Asm.getContext().FatalError(Fixup.getLoc(),
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"symbol '" + B->getSymbol().getName() +
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"' can not be undefined in a subtraction expression");
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// Select the appropriate difference relocation type.
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Type = macho::RIT_Difference;
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Value2 = Writer->getSymbolAddress(B_SD, Layout);
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FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent());
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}
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// Relocations are written out in reverse order, so the PAIR comes first.
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if (Type == macho::RIT_Difference ||
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Type == macho::RIT_Generic_LocalDifference) {
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macho::RelocationEntry MRE;
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MRE.Word0 = ((0 << 0) |
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(macho::RIT_Pair << 24) |
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(Log2Size << 28) |
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(IsPCRel << 30) |
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macho::RF_Scattered);
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MRE.Word1 = Value2;
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Writer->addRelocation(Fragment->getParent(), MRE);
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}
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macho::RelocationEntry MRE;
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MRE.Word0 = ((FixupOffset << 0) |
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(Type << 24) |
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(Log2Size << 28) |
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(IsPCRel << 30) |
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macho::RF_Scattered);
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MRE.Word1 = Value;
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Writer->addRelocation(Fragment->getParent(), MRE);
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}
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bool ARMMachObjectWriter::requiresExternRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm,
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const MCFragment &Fragment,
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unsigned RelocType,
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const MCSymbolData *SD,
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uint64_t FixedValue) {
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// Most cases can be identified purely from the symbol.
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if (Writer->doesSymbolRequireExternRelocation(SD))
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return true;
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int64_t Value = (int64_t)FixedValue; // The displacement is signed.
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int64_t Range;
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switch (RelocType) {
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default:
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return false;
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case macho::RIT_ARM_Branch24Bit:
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// PC pre-adjustment of 8 for these instructions.
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Value -= 8;
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// ARM BL/BLX has a 25-bit offset.
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Range = 0x1ffffff;
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break;
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case macho::RIT_ARM_ThumbBranch22Bit:
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// PC pre-adjustment of 4 for these instructions.
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Value -= 4;
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// Thumb BL/BLX has a 24-bit offset.
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Range = 0xffffff;
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}
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// BL/BLX also use external relocations when an internal relocation
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// would result in the target being out of range. This gives the linker
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// enough information to generate a branch island.
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const MCSectionData &SymSD = Asm.getSectionData(
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SD->getSymbol().getSection());
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Value += Writer->getSectionAddress(&SymSD);
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Value -= Writer->getSectionAddress(Fragment.getParent());
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// If the resultant value would be out of range for an internal relocation,
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// use an external instead.
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if (Value > Range || Value < -(Range + 1))
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return true;
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return false;
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}
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void ARMMachObjectWriter::RecordRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFragment *Fragment,
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const MCFixup &Fixup,
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MCValue Target,
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uint64_t &FixedValue) {
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unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
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unsigned Log2Size;
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unsigned RelocType = macho::RIT_Vanilla;
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if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size))
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// If we failed to get fixup kind info, it's because there's no legal
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// relocation type for the fixup kind. This happens when it's a fixup that's
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// expected to always be resolvable at assembly time and not have any
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// relocations needed.
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Asm.getContext().FatalError(Fixup.getLoc(),
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"unsupported relocation on symbol");
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// If this is a difference or a defined symbol plus an offset, then we need a
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// scattered relocation entry. Differences always require scattered
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// relocations.
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if (Target.getSymB()) {
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if (RelocType == macho::RIT_ARM_Half)
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return RecordARMScatteredHalfRelocation(Writer, Asm, Layout, Fragment,
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Fixup, Target, FixedValue);
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return RecordARMScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
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Target, Log2Size, FixedValue);
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}
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// Get the symbol data, if any.
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MCSymbolData *SD = 0;
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if (Target.getSymA())
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SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
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// FIXME: For other platforms, we need to use scattered relocations for
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// internal relocations with offsets. If this is an internal relocation with
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// an offset, it also needs a scattered relocation entry.
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//
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// Is this right for ARM?
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uint32_t Offset = Target.getConstant();
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if (IsPCRel && RelocType == macho::RIT_Vanilla)
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Offset += 1 << Log2Size;
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if (Offset && SD && !Writer->doesSymbolRequireExternRelocation(SD))
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return RecordARMScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
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Target, Log2Size, FixedValue);
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// See <reloc.h>.
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uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
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unsigned Index = 0;
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unsigned IsExtern = 0;
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unsigned Type = 0;
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if (Target.isAbsolute()) { // constant
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// FIXME!
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report_fatal_error("FIXME: relocations to absolute targets "
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"not yet implemented");
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} else {
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// Resolve constant variables.
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if (SD->getSymbol().isVariable()) {
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int64_t Res;
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if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
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Res, Layout, Writer->getSectionAddressMap())) {
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FixedValue = Res;
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return;
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}
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}
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// Check whether we need an external or internal relocation.
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if (requiresExternRelocation(Writer, Asm, *Fragment, RelocType, SD,
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FixedValue)) {
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IsExtern = 1;
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Index = SD->getIndex();
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// For external relocations, make sure to offset the fixup value to
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// compensate for the addend of the symbol address, if it was
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// undefined. This occurs with weak definitions, for example.
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if (!SD->Symbol->isUndefined())
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FixedValue -= Layout.getSymbolOffset(SD);
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} else {
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// The index is the section ordinal (1-based).
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const MCSectionData &SymSD = Asm.getSectionData(
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SD->getSymbol().getSection());
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Index = SymSD.getOrdinal() + 1;
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FixedValue += Writer->getSectionAddress(&SymSD);
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}
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if (IsPCRel)
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FixedValue -= Writer->getSectionAddress(Fragment->getParent());
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// The type is determined by the fixup kind.
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Type = RelocType;
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}
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// struct relocation_info (8 bytes)
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macho::RelocationEntry MRE;
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MRE.Word0 = FixupOffset;
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MRE.Word1 = ((Index << 0) |
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(IsPCRel << 24) |
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(Log2Size << 25) |
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(IsExtern << 27) |
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(Type << 28));
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// Even when it's not a scattered relocation, movw/movt always uses
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// a PAIR relocation.
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if (Type == macho::RIT_ARM_Half) {
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// The other-half value only gets populated for the movt and movw
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// relocation entries.
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uint32_t Value = 0;
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switch ((unsigned)Fixup.getKind()) {
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default: break;
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case ARM::fixup_arm_movw_lo16:
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case ARM::fixup_arm_movw_lo16_pcrel:
|
|
case ARM::fixup_t2_movw_lo16:
|
|
case ARM::fixup_t2_movw_lo16_pcrel:
|
|
Value = (FixedValue >> 16) & 0xffff;
|
|
break;
|
|
case ARM::fixup_arm_movt_hi16:
|
|
case ARM::fixup_arm_movt_hi16_pcrel:
|
|
case ARM::fixup_t2_movt_hi16:
|
|
case ARM::fixup_t2_movt_hi16_pcrel:
|
|
Value = FixedValue & 0xffff;
|
|
break;
|
|
}
|
|
macho::RelocationEntry MREPair;
|
|
MREPair.Word0 = Value;
|
|
MREPair.Word1 = ((0xffffff) |
|
|
(Log2Size << 25) |
|
|
(macho::RIT_Pair << 28));
|
|
|
|
Writer->addRelocation(Fragment->getParent(), MREPair);
|
|
}
|
|
|
|
Writer->addRelocation(Fragment->getParent(), MRE);
|
|
}
|
|
|
|
MCObjectWriter *llvm::createARMMachObjectWriter(raw_ostream &OS,
|
|
bool Is64Bit,
|
|
uint32_t CPUType,
|
|
uint32_t CPUSubtype) {
|
|
return createMachObjectWriter(new ARMMachObjectWriter(Is64Bit,
|
|
CPUType,
|
|
CPUSubtype),
|
|
OS, /*IsLittleEndian=*/true);
|
|
}
|