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587daedce2
booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
278 lines
10 KiB
C++
278 lines
10 KiB
C++
//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInstrInfo.h"
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#include "SparcSubtarget.h"
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#include "Sparc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "SparcGenInstrInfo.inc"
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using namespace llvm;
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SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
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: TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
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RI(ST, *this), Subtarget(ST) {
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}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSR, unsigned &DstSR) const {
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SrcSR = DstSR = 0; // No sub-registers.
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// We look for 3 kinds of patterns here:
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// or with G0 or 0
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// add with G0 or 0
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// fmovs or FpMOVD (pseudo double move).
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if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
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if (MI.getOperand(1).getReg() == SP::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (MI.getOperand(2).getReg() == SP::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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} else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
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isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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} else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
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MI.getOpcode() == SP::FMOVD) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::LDri ||
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MI->getOpcode() == SP::LDFri ||
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MI->getOpcode() == SP::LDDFri) {
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if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::STri ||
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MI->getOpcode() == SP::STFri ||
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MI->getOpcode() == SP::STDFri) {
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if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
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MI->getOperand(1).getImm() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(2).getReg();
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}
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}
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return 0;
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}
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unsigned
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SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond)const{
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// FIXME this should probably take a DebugLoc argument
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DebugLoc dl = DebugLoc::getUnknownLoc();
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
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return 1;
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}
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bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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// Not yet supported!
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return false;
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}
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
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else if (DestRC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg);
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else if (DestRC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
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.addReg(SrcReg);
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else
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// Can't copy this register
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return false;
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return true;
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}
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void SparcInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else if (RC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else if (RC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else
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assert(0 && "Can't store this register to stack slot");
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}
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void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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unsigned Opc = 0;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (RC == SP::IntRegsRegisterClass)
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Opc = SP::STri;
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else if (RC == SP::FPRegsRegisterClass)
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Opc = SP::STFri;
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else if (RC == SP::DFPRegsRegisterClass)
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Opc = SP::STDFri;
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else
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assert(0 && "Can't load this register");
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
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for (unsigned i = 0, e = Addr.size(); i != e; ++i)
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MIB.addOperand(Addr[i]);
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MIB.addReg(SrcReg, getKillRegState(isKill));
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NewMIs.push_back(MIB);
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return;
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}
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void SparcInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
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else
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assert(0 && "Can't load this register from stack slot");
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}
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void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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unsigned Opc = 0;
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if (RC == SP::IntRegsRegisterClass)
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Opc = SP::LDri;
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else if (RC == SP::FPRegsRegisterClass)
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Opc = SP::LDFri;
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else if (RC == SP::DFPRegsRegisterClass)
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Opc = SP::LDDFri;
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else
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assert(0 && "Can't load this register");
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DebugLoc DL = DebugLoc::getUnknownLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i)
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MIB.addOperand(Addr[i]);
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NewMIs.push_back(MIB);
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return;
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}
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MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FI) const {
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if (Ops.size() != 1) return NULL;
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unsigned OpNum = Ops[0];
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bool isFloat = false;
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MachineInstr *NewMI = NULL;
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switch (MI->getOpcode()) {
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case SP::ORrr:
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if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
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MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
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if (OpNum == 0) // COPY -> STORE
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
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.addFrameIndex(FI)
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.addImm(0)
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.addReg(MI->getOperand(2).getReg());
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else // COPY -> LOAD
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
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MI->getOperand(0).getReg())
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.addFrameIndex(FI)
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.addImm(0);
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}
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break;
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case SP::FMOVS:
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isFloat = true;
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// FALLTHROUGH
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case SP::FMOVD:
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if (OpNum == 0) { // COPY -> STORE
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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NewMI = BuildMI(MF, MI->getDebugLoc(),
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get(isFloat ? SP::STFri : SP::STDFri))
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.addFrameIndex(FI)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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} else { // COPY -> LOAD
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unsigned DstReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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NewMI = BuildMI(MF, MI->getDebugLoc(),
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get(isFloat ? SP::LDFri : SP::LDDFri))
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.addReg(DstReg, RegState::Define | getDeadRegState(isDead))
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.addFrameIndex(FI)
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.addImm(0);
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}
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break;
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}
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return NewMI;
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}
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