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https://github.com/c64scene-ar/llvm-6502.git
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420736dc85
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
604 lines
17 KiB
Plaintext
604 lines
17 KiB
Plaintext
TODO:
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* gpr0 allocation
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* implement do-loop -> bdnz transform
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* implement powerpc-64 for darwin
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===-------------------------------------------------------------------------===
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Support 'update' load/store instructions. These are cracked on the G5, but are
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still a codesize win.
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===-------------------------------------------------------------------------===
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Teach the .td file to pattern match PPC::BR_COND to appropriate bc variant, so
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we don't have to always run the branch selector for small functions.
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===-------------------------------------------------------------------------===
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* Codegen this:
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void test2(int X) {
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if (X == 0x12345678) bar();
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}
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as:
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xoris r0,r3,0x1234
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cmplwi cr0,r0,0x5678
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beq cr0,L6
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not:
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lis r2, 4660
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ori r2, r2, 22136
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cmpw cr0, r3, r2
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bne .LBB_test2_2
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===-------------------------------------------------------------------------===
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Lump the constant pool for each function into ONE pic object, and reference
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pieces of it as offsets from the start. For functions like this (contrived
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to have lots of constants obviously):
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double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
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We generate:
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_X:
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lis r2, ha16(.CPI_X_0)
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lfd f0, lo16(.CPI_X_0)(r2)
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lis r2, ha16(.CPI_X_1)
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lfd f2, lo16(.CPI_X_1)(r2)
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fmadd f0, f1, f0, f2
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lis r2, ha16(.CPI_X_2)
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lfd f1, lo16(.CPI_X_2)(r2)
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lis r2, ha16(.CPI_X_3)
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lfd f2, lo16(.CPI_X_3)(r2)
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fmadd f1, f0, f1, f2
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blr
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It would be better to materialize .CPI_X into a register, then use immediates
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off of the register to avoid the lis's. This is even more important in PIC
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mode.
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Note that this (and the static variable version) is discussed here for GCC:
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http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
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===-------------------------------------------------------------------------===
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PIC Code Gen IPO optimization:
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Squish small scalar globals together into a single global struct, allowing the
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address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
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of the GOT on targets with one).
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Note that this is discussed here for GCC:
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http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
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===-------------------------------------------------------------------------===
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Implement Newton-Rhapson method for improving estimate instructions to the
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correct accuracy, and implementing divide as multiply by reciprocal when it has
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more than one use. Itanium will want this too.
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===-------------------------------------------------------------------------===
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#define ARRAY_LENGTH 16
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union bitfield {
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struct {
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#ifndef __ppc__
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unsigned int field0 : 6;
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unsigned int field1 : 6;
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unsigned int field2 : 6;
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unsigned int field3 : 6;
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unsigned int field4 : 3;
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unsigned int field5 : 4;
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unsigned int field6 : 1;
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#else
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unsigned int field6 : 1;
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unsigned int field5 : 4;
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unsigned int field4 : 3;
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unsigned int field3 : 6;
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unsigned int field2 : 6;
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unsigned int field1 : 6;
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unsigned int field0 : 6;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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typedef struct program_t {
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union bitfield array[ARRAY_LENGTH];
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int size;
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int loaded;
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} program;
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void AdjustBitfields(program* prog, unsigned int fmt1)
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{
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prog->array[0].bitfields.field0 = fmt1;
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prog->array[0].bitfields.field1 = fmt1 + 1;
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}
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We currently generate:
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_AdjustBitfields:
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lwz r2, 0(r3)
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addi r5, r4, 1
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rlwinm r2, r2, 0, 0, 19
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rlwinm r5, r5, 6, 20, 25
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rlwimi r2, r4, 0, 26, 31
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or r2, r2, r5
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stw r2, 0(r3)
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blr
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We should teach someone that or (rlwimi, rlwinm) with disjoint masks can be
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turned into rlwimi (rlwimi)
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The better codegen would be:
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_AdjustBitfields:
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lwz r0,0(r3)
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rlwinm r4,r4,0,0xff
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rlwimi r0,r4,0,26,31
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addi r4,r4,1
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rlwimi r0,r4,6,20,25
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stw r0,0(r3)
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blr
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===-------------------------------------------------------------------------===
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Compile this:
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int %f1(int %a, int %b) {
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%tmp.1 = and int %a, 15 ; <int> [#uses=1]
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%tmp.3 = and int %b, 240 ; <int> [#uses=1]
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%tmp.4 = or int %tmp.3, %tmp.1 ; <int> [#uses=1]
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ret int %tmp.4
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}
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without a copy. We make this currently:
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_f1:
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rlwinm r2, r4, 0, 24, 27
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rlwimi r2, r3, 0, 28, 31
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or r3, r2, r2
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blr
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The two-addr pass or RA needs to learn when it is profitable to commute an
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instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
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currently only commutes to avoid inserting a copy BEFORE the two addr instr.
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===-------------------------------------------------------------------------===
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Compile offsets from allocas:
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int *%test() {
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%X = alloca { int, int }
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%Y = getelementptr {int,int}* %X, int 0, uint 1
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ret int* %Y
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}
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into a single add, not two:
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_test:
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addi r2, r1, -8
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addi r3, r2, 4
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blr
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--> important for C++.
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===-------------------------------------------------------------------------===
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int test3(int a, int b) { return (a < 0) ? a : 0; }
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should be branch free code. LLVM is turning it into < 1 because of the RHS.
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===-------------------------------------------------------------------------===
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No loads or stores of the constants should be needed:
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struct foo { double X, Y; };
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void xxx(struct foo F);
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void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
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===-------------------------------------------------------------------------===
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Darwin Stub LICM optimization:
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Loops like this:
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for (...) bar();
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Have to go through an indirect stub if bar is external or linkonce. It would
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be better to compile it as:
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fp = &bar;
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for (...) fp();
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which only computes the address of bar once (instead of each time through the
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stub). This is Darwin specific and would have to be done in the code generator.
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Probably not a win on x86.
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===-------------------------------------------------------------------------===
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PowerPC i1/setcc stuff (depends on subreg stuff):
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Check out the PPC code we get for 'compare' in this testcase:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19672
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oof. on top of not doing the logical crnand instead of (mfcr, mfcr,
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invert, invert, or), we then have to compare it against zero instead of
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using the value already in a CR!
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that should be something like
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cmpw cr7, r8, r5
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cmpw cr0, r7, r3
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crnand cr0, cr0, cr7
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bne cr0, LBB_compare_4
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instead of
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cmpw cr7, r8, r5
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cmpw cr0, r7, r3
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mfcr r7, 1
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mcrf cr7, cr0
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mfcr r8, 1
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rlwinm r7, r7, 30, 31, 31
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rlwinm r8, r8, 30, 31, 31
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xori r7, r7, 1
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xori r8, r8, 1
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addi r2, r2, 1
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or r7, r8, r7
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cmpwi cr0, r7, 0
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bne cr0, LBB_compare_4 ; loopexit
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FreeBench/mason has a basic block that looks like this:
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%tmp.130 = seteq int %p.0__, 5 ; <bool> [#uses=1]
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%tmp.134 = seteq int %p.1__, 6 ; <bool> [#uses=1]
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%tmp.139 = seteq int %p.2__, 12 ; <bool> [#uses=1]
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%tmp.144 = seteq int %p.3__, 13 ; <bool> [#uses=1]
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%tmp.149 = seteq int %p.4__, 14 ; <bool> [#uses=1]
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%tmp.154 = seteq int %p.5__, 15 ; <bool> [#uses=1]
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%bothcond = and bool %tmp.134, %tmp.130 ; <bool> [#uses=1]
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%bothcond123 = and bool %bothcond, %tmp.139 ; <bool>
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%bothcond124 = and bool %bothcond123, %tmp.144 ; <bool>
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%bothcond125 = and bool %bothcond124, %tmp.149 ; <bool>
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%bothcond126 = and bool %bothcond125, %tmp.154 ; <bool>
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br bool %bothcond126, label %shortcirc_next.5, label %else.0
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This is a particularly important case where handling CRs better will help.
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===-------------------------------------------------------------------------===
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Simple IPO for argument passing, change:
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void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
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the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
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of arguments get assigned to r3 through r10. That is, if you have a function
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foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
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argument bytes for r4 and r5. The trick then would be to shuffle the argument
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order for functions we can internalize so that the maximum number of
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integers/pointers get passed in regs before you see any of the fp arguments.
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Instead of implementing this, it would actually probably be easier to just
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implement a PPC fastcc, where we could do whatever we wanted to the CC,
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including having this work sanely.
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===-------------------------------------------------------------------------===
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Fix Darwin FP-In-Integer Registers ABI
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Darwin passes doubles in structures in integer registers, which is very very
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bad. Add something like a BIT_CONVERT to LLVM, then do an i-p transformation
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that percolates these things out of functions.
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Check out how horrible this is:
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http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
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This is an extension of "interprocedural CC unmunging" that can't be done with
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just fastcc.
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===-------------------------------------------------------------------------===
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Generate lwbrx and other byteswapping load/store instructions when reasonable.
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===-------------------------------------------------------------------------===
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Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
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TargetConstantVec's if it's one of the many forms that are algorithmically
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computable using the spiffy altivec instructions.
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===-------------------------------------------------------------------------===
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Compile this:
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int foo(int a) {
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int b = (a < 8);
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if (b) {
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return b * 3; // ignore the fact that this is always 3.
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} else {
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return 2;
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}
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}
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into something not this:
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_foo:
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1) cmpwi cr7, r3, 8
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mfcr r2, 1
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rlwinm r2, r2, 29, 31, 31
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1) cmpwi cr0, r3, 7
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bgt cr0, LBB1_2 ; UnifiedReturnBlock
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LBB1_1: ; then
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rlwinm r2, r2, 0, 31, 31
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mulli r3, r2, 3
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blr
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LBB1_2: ; UnifiedReturnBlock
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li r3, 2
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blr
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In particular, the two compares (marked 1) could be shared by reversing one.
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This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
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same operands (but backwards) exists. In this case, this wouldn't save us
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anything though, because the compares still wouldn't be shared.
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===-------------------------------------------------------------------------===
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The legalizer should lower this:
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bool %test(ulong %x) {
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%tmp = setlt ulong %x, 4294967296
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ret bool %tmp
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}
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into "if x.high == 0", not:
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_test:
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addi r2, r3, -1
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cntlzw r2, r2
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cntlzw r3, r3
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srwi r2, r2, 5
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srwi r4, r3, 5
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li r3, 0
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cmpwi cr0, r2, 0
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bne cr0, LBB1_2 ;
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LBB1_1:
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or r3, r4, r4
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LBB1_2:
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blr
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noticed in 2005-05-11-Popcount-ffs-fls.c.
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===-------------------------------------------------------------------------===
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We should custom expand setcc instead of pretending that we have it. That
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would allow us to expose the access of the crbit after the mfcr, allowing
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that access to be trivially folded into other ops. A simple example:
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int foo(int a, int b) { return (a < b) << 4; }
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compiles into:
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_foo:
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cmpw cr7, r3, r4
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mfcr r2, 1
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rlwinm r2, r2, 29, 31, 31
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slwi r3, r2, 4
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blr
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===-------------------------------------------------------------------------===
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Fold add and sub with constant into non-extern, non-weak addresses so this:
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static int a;
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void bar(int b) { a = b; }
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void foo(unsigned char *c) {
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*c = a;
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}
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So that
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_foo:
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lis r2, ha16(_a)
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la r2, lo16(_a)(r2)
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lbz r2, 3(r2)
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stb r2, 0(r3)
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blr
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Becomes
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_foo:
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lis r2, ha16(_a+3)
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lbz r2, lo16(_a+3)(r2)
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stb r2, 0(r3)
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blr
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===-------------------------------------------------------------------------===
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We generate really bad code for this:
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int f(signed char *a, _Bool b, _Bool c) {
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signed char t = 0;
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if (b) t = *a;
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if (c) *a = t;
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}
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===-------------------------------------------------------------------------===
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This:
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int test(unsigned *P) { return *P >> 24; }
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Should compile to:
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_test:
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lbz r3,0(r3)
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blr
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not:
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_test:
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lwz r2, 0(r3)
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srwi r3, r2, 24
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blr
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===-------------------------------------------------------------------------===
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On the G5, logical CR operations are more expensive in their three
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address form: ops that read/write the same register are half as expensive as
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those that read from two registers that are different from their destination.
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We should model this with two separate instructions. The isel should generate
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the "two address" form of the instructions. When the register allocator
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detects that it needs to insert a copy due to the two-addresness of the CR
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logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point
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we can convert to the "three address" instruction, to save code space.
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This only matters when we start generating cr logical ops.
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===-------------------------------------------------------------------------===
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We should compile these two functions to the same thing:
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#include <stdlib.h>
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void f(int a, int b, int *P) {
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*P = (a-b)>=0?(a-b):(b-a);
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}
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void g(int a, int b, int *P) {
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*P = abs(a-b);
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}
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Further, they should compile to something better than:
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_g:
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subf r2, r4, r3
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subfic r3, r2, 0
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cmpwi cr0, r2, -1
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bgt cr0, LBB2_2 ; entry
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LBB2_1: ; entry
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mr r2, r3
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LBB2_2: ; entry
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stw r2, 0(r5)
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blr
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GCC produces:
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_g:
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subf r4,r4,r3
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srawi r2,r4,31
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xor r0,r2,r4
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subf r0,r2,r0
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stw r0,0(r5)
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blr
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... which is much nicer.
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This theoretically may help improve twolf slightly (used in dimbox.c:142?).
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===-------------------------------------------------------------------------===
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Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
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registers, to generate better spill code.
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===-------------------------------------------------------------------------===
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int foo(int N, int ***W, int **TK, int X) {
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int t, i;
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for (t = 0; t < N; ++t)
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for (i = 0; i < 4; ++i)
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W[t / X][i][t % X] = TK[i][t];
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return 5;
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}
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We generate relatively atrocious code for this loop compared to gcc.
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We could also strength reduce the rem and the div:
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http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
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===-------------------------------------------------------------------------===
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Altivec support. The first should be a single lvx from the constant pool, the
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second should be a xor/stvx:
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void foo(void) {
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int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
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bar (x);
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}
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#include <string.h>
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void foo(void) {
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int x[8] __attribute__((aligned(128)));
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memset (x, 0, sizeof (x));
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bar (x);
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}
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===-------------------------------------------------------------------------===
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Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
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We need to codegen -0.0 vector efficiently (no constant pool load).
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When -ffast-math is on, we can use 0.0.
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===-------------------------------------------------------------------------===
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float foo(float X) { return (int)(X); }
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Currently produces:
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_foo:
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fctiwz f0, f1
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stfd f0, -8(r1)
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lwz r2, -4(r1)
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extsw r2, r2
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std r2, -16(r1)
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lfd f0, -16(r1)
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fcfid f0, f0
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frsp f1, f0
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blr
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We could use a target dag combine to turn the lwz/extsw into an lwa when the
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lwz has a single use. Since LWA is cracked anyway, this would be a codesize
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win only.
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===-------------------------------------------------------------------------===
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Consider this:
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v4f32 Vector;
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v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
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Since we know that "Vector" is 16-byte aligned and we know the element offset
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of ".X", we should change the load into a lve*x instruction, instead of doing
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a load/store/lve*x sequence.
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===-------------------------------------------------------------------------===
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We generate ugly code for this:
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void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
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unsigned code = 0;
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if(dx < -dw) code |= 1;
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if(dx > dw) code |= 2;
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if(dy < -dw) code |= 4;
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if(dy > dw) code |= 8;
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if(dz < -dw) code |= 16;
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if(dz > dw) code |= 32;
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*ret = code;
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}
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===-------------------------------------------------------------------------===
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There are a wide range of vector constants we can generate with combinations of
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altivec instructions. For example, GCC does: t=vsplti*, r = t+t.
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===-------------------------------------------------------------------------===
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