llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-16 11:30:51 +00:00

History

Jakob Stoklund Olesen 2a9d1ca9c2 Remove custom allocation order boilerplate that is no longer needed. The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8		2011-06-09 16:56:59 +00:00
..
TargetInfo
Alpha.h
Alpha.td	Fix a ton of comment typos found by codespell. Patch by	2011-04-15 05:18:47 +00:00
AlphaAsmPrinter.cpp
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp
AlphaFrameLowering.h
AlphaInstrFormats.td
AlphaInstrInfo.cpp
AlphaInstrInfo.h
AlphaInstrInfo.td	Fix a ton of comment typos found by codespell. Patch by	2011-04-15 05:18:47 +00:00
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp	Add a parameter to CCState so that it can access the MachineFunction.	2011-06-08 23:55:35 +00:00
AlphaISelLowering.h	Make the logic for determining function alignment more explicit. No functionality change.	2011-05-06 20:34:06 +00:00
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp	Use the dwarf->llvm mapping to print register names in the cfi	2011-05-30 20:20:15 +00:00
AlphaRegisterInfo.h	Use the dwarf->llvm mapping to print register names in the cfi	2011-05-30 20:20:15 +00:00
AlphaRegisterInfo.td	Remove custom allocation order boilerplate that is no longer needed.	2011-06-09 16:56:59 +00:00
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h
CMakeLists.txt
Makefile
README.txt	Fix a ton of comment typos found by codespell. Patch by	2011-04-15 05:18:47 +00:00

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html