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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22896 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
4.6 KiB
C++
138 lines
4.6 KiB
C++
//===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple code linearizer for DAGs. This is not a very good
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// way to emit code, but gets working code quickly.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#ifndef _NDEBUG
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static cl::opt<bool>
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ViewDAGs("view-sched-dags", cl::Hidden,
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cl::desc("Pop up a window to show sched dags as they are processed"));
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#else
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static const bool ViewDAGS = 0;
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#endif
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namespace {
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class SimpleSched {
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SelectionDAG &DAG;
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MachineBasicBlock *BB;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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std::map<SDNode *, unsigned> EmittedOps;
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public:
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SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
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: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()) {
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assert(&TII && "Target doesn't provide instr info?");
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}
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void Run() {
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Emit(DAG.getRoot());
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}
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private:
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unsigned Emit(SDOperand Op);
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};
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}
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unsigned SimpleSched::Emit(SDOperand Op) {
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// Check to see if we have already emitted this. If so, return the value
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// already emitted. Note that if a node has a single use it cannot be
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// revisited, so don't bother putting it in the map.
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unsigned *OpSlot;
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if (Op.Val->hasOneUse()) {
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OpSlot = 0; // No reuse possible.
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} else {
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std::map<SDNode *, unsigned>::iterator OpI = EmittedOps.lower_bound(Op.Val);
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if (OpI != EmittedOps.end() && OpI->first == Op.Val)
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return OpI->second + Op.ResNo;
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OpSlot = &EmittedOps.insert(OpI, std::make_pair(Op.Val, 0))->second;
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}
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unsigned ResultReg = 0;
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if (Op.isTargetOpcode()) {
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unsigned Opc = Op.getTargetOpcode();
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const TargetInstrDescriptor &II = TII.get(Opc);
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// Target nodes have any register or immediate operands before any chain
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// nodes. Check that the DAG matches the TD files's expectation of #
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// operands.
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#ifndef _NDEBUG
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unsigned Operands = Op.getNumOperands();
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if (Operands && Op.getOperand(Operands-1).getValueType() == MVT::Other)
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--Operands;
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unsigned Results = Op.Val->getNumValues();
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if (Results && Op.getOperand(Results-1).getValueType() == MVT::Other)
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--Results;
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assert(unsigned(II.numOperands) == Operands+Results &&
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = new MachineInstr(Opc, II.numOperands, true, true);
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// Add result register values for things that are defined by this
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// instruction.
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assert(Op.Val->getNumValues() == 1 &&
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Op.getValue(0).getValueType() == MVT::Other &&
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"Return values not implemented yet");
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// Emit all of the operands of this instruction, adding them to the
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// instruction as appropriate.
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for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
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MI->addZeroExtImm64Operand(C->getValue());
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} else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
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MI->addRegOperand(R->getReg(), MachineOperand::Use);
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} else {
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unsigned R = Emit(Op.getOperand(i));
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// Add an operand, unless this corresponds to a chain node.
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if (Op.getOperand(i).getValueType() != MVT::Other)
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MI->addRegOperand(R, MachineOperand::Use);
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}
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}
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// Now that we have emitted all operands, emit this instruction itself.
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BB->insert(BB->end(), MI);
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} else {
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switch (Op.getOpcode()) {
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default:
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Op.Val->dump();
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: break;
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case ISD::CopyToReg: {
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unsigned Val = Emit(Op.getOperand(2));
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// FIXME: DO THE COPY NOW.
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break;
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}
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}
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}
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if (OpSlot) *OpSlot = ResultReg;
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return ResultReg+Op.ResNo;
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}
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
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if (ViewDAGs) SD.viewGraph();
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SimpleSched(SD, BB).Run();
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}
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