mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2f1abe2dae
can access the hi regs. Our prologue and epilogue code doesn't know how to properly handle save/restore of the hi regs, so things go badly when we alloc them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
404 lines
16 KiB
C++
404 lines
16 KiB
C++
//===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the ARM register file
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//===----------------------------------------------------------------------===//
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// Registers are identified with 4-bit ID numbers.
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class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
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field bits<4> Num;
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let Namespace = "ARM";
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let SubRegs = subregs;
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}
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class ARMFReg<bits<6> num, string n> : Register<n> {
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field bits<6> Num;
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let Namespace = "ARM";
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}
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// Integer registers
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def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
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def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
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def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
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def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
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def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
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def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
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def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
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def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
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// Float registers
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def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
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def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
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def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
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def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
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def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
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def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
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def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
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def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
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def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
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def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
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def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
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def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
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def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
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def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
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def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
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def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
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def SDummy : ARMFReg<63, "sINVALID">;
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// Aliases of the F* registers used to hold 64-bit fp values (doubles)
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def D0 : ARMReg< 0, "d0", [S0, S1]>;
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def D1 : ARMReg< 1, "d1", [S2, S3]>;
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def D2 : ARMReg< 2, "d2", [S4, S5]>;
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def D3 : ARMReg< 3, "d3", [S6, S7]>;
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def D4 : ARMReg< 4, "d4", [S8, S9]>;
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def D5 : ARMReg< 5, "d5", [S10, S11]>;
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def D6 : ARMReg< 6, "d6", [S12, S13]>;
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def D7 : ARMReg< 7, "d7", [S14, S15]>;
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def D8 : ARMReg< 8, "d8", [S16, S17]>;
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def D9 : ARMReg< 9, "d9", [S18, S19]>;
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def D10 : ARMReg<10, "d10", [S20, S21]>;
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def D11 : ARMReg<11, "d11", [S22, S23]>;
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def D12 : ARMReg<12, "d12", [S24, S25]>;
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def D13 : ARMReg<13, "d13", [S26, S27]>;
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def D14 : ARMReg<14, "d14", [S28, S29]>;
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def D15 : ARMReg<15, "d15", [S30, S31]>;
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// VFP3 defines 16 additional double registers
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def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">;
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def D18 : ARMFReg<18, "d18">; def D19 : ARMFReg<19, "d19">;
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def D20 : ARMFReg<20, "d20">; def D21 : ARMFReg<21, "d21">;
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def D22 : ARMFReg<22, "d22">; def D23 : ARMFReg<23, "d23">;
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def D24 : ARMFReg<24, "d24">; def D25 : ARMFReg<25, "d25">;
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def D26 : ARMFReg<26, "d26">; def D27 : ARMFReg<27, "d27">;
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def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">;
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def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">;
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// Advanced SIMD (NEON) defines 16 quad-word aliases
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def Q0 : ARMReg< 0, "q0", [D0, D1]>;
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def Q1 : ARMReg< 1, "q1", [D2, D3]>;
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def Q2 : ARMReg< 2, "q2", [D4, D5]>;
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def Q3 : ARMReg< 3, "q3", [D6, D7]>;
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def Q4 : ARMReg< 4, "q4", [D8, D9]>;
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def Q5 : ARMReg< 5, "q5", [D10, D11]>;
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def Q6 : ARMReg< 6, "q6", [D12, D13]>;
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def Q7 : ARMReg< 7, "q7", [D14, D15]>;
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def Q8 : ARMReg< 8, "q8", [D16, D17]>;
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def Q9 : ARMReg< 9, "q9", [D18, D19]>;
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def Q10 : ARMReg<10, "q10", [D20, D21]>;
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def Q11 : ARMReg<11, "q11", [D22, D23]>;
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def Q12 : ARMReg<12, "q12", [D24, D25]>;
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def Q13 : ARMReg<13, "q13", [D26, D27]>;
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def Q14 : ARMReg<14, "q14", [D28, D29]>;
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def Q15 : ARMReg<15, "q15", [D30, D31]>;
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// Current Program Status Register.
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def CPSR : ARMReg<0, "cpsr">;
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def FPSCR : ARMReg<1, "fpscr">;
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// Register classes.
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//
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// pc == Program Counter
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// lr == Link Register
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// sp == Stack Pointer
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// r12 == ip (scratch)
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// r7 == Frame Pointer (thumb-style backtraces)
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// r9 == May be reserved as Thread Register
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// r11 == Frame Pointer (arm-style backtraces)
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// r10 == Stack Limit
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//
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def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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R7, R8, R9, R10, R12, R11,
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LR, SP, PC]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// FP is R11, R9 is available.
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static const unsigned ARM_GPR_AO_1[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10,
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ARM::R11 };
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// FP is R11, R9 is not available.
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static const unsigned ARM_GPR_AO_2[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R10,
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ARM::R11 };
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// FP is R7, R9 is available as non-callee-saved register.
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// This is used by Darwin.
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static const unsigned ARM_GPR_AO_3[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R9, ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6,
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ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
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// FP is R7, R9 is not available.
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static const unsigned ARM_GPR_AO_4[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6,
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ARM::R8, ARM::R10,ARM::R11,
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ARM::R7 };
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// FP is R7, R9 is available as callee-saved register.
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// This is used by non-Darwin platform in Thumb mode.
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static const unsigned ARM_GPR_AO_5[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6,
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ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we
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// don't know how to spill them. If we make our prologue/epilogue code
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// smarter at some point, we can go back to using the above allocation
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// orders for the Thumb1 instructions that know how to use hi regs.
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static const unsigned THUMB_GPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
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GPRClass::iterator
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GPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO;
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if (Subtarget.isTargetDarwin()) {
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if (Subtarget.isR9Reserved())
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return ARM_GPR_AO_4;
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else
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return ARM_GPR_AO_3;
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} else {
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if (Subtarget.isR9Reserved())
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return ARM_GPR_AO_2;
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else if (Subtarget.isThumb())
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return ARM_GPR_AO_5;
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else
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return ARM_GPR_AO_1;
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}
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}
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GPRClass::iterator
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GPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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GPRClass::iterator I;
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if (Subtarget.isThumb1Only()) {
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I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
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// Mac OS X requires FP not to be clobbered for backtracing purpose.
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return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
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}
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if (Subtarget.isTargetDarwin()) {
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if (Subtarget.isR9Reserved())
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I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
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else
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I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
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} else {
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if (Subtarget.isR9Reserved())
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I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
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else if (Subtarget.isThumb())
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I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
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else
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I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
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}
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// Mac OS X requires FP not to be clobbered for backtracing purpose.
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return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
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}
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}];
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}
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// Thumb registers are R0-R7 normally. Some instructions can still use
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// the general GPR register class above (MOV, e.g.)
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def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned THUMB_tGPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
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// FP is R7, only low registers available.
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tGPRClass::iterator
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tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
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return THUMB_tGPR_AO;
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}
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tGPRClass::iterator
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tGPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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tGPRClass::iterator I =
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THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
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// Mac OS X requires FP not to be clobbered for backtracing purpose.
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return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
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}
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}];
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}
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// Scalar single precision floating point register class..
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def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
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S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
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// Subset of SPR which can be used as a source of NEON scalars for 16-bit
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// operations
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def SPR_8 : RegisterClass<"ARM", [f32], 32,
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[S0, S1, S2, S3, S4, S5, S6, S7,
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S8, S9, S10, S11, S12, S13, S14, S15]>;
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// Dummy f32 regclass to represent impossible subreg indices.
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def SPR_INVALID : RegisterClass<"ARM", [f32], 32, [SDummy]> {
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let CopyCost = -1;
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}
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// Scalar double precision floating point / generic 64-bit vector register
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// class.
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// ARM requires only word alignment for double. It's more performant if it
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// is double-word alignment though.
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def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
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[D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31]> {
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let SubRegClassList = [SPR_INVALID, SPR_INVALID];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// VFP2
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static const unsigned ARM_DPR_VFP2[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
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// VFP3
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static const unsigned ARM_DPR_VFP3[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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ARM::D12, ARM::D13, ARM::D14, ARM::D15,
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ARM::D16, ARM::D17, ARM::D18, ARM::D19,
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ARM::D20, ARM::D21, ARM::D22, ARM::D23,
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ARM::D24, ARM::D25, ARM::D26, ARM::D27,
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ARM::D28, ARM::D29, ARM::D30, ARM::D31 };
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DPRClass::iterator
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DPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.hasVFP3())
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return ARM_DPR_VFP3;
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return ARM_DPR_VFP2;
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}
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DPRClass::iterator
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DPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.hasVFP3())
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return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
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else
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return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
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}
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}];
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}
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// Subset of DPR that are accessible with VFP2 (and so that also have
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// 32-bit SPR subregs).
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def DPR_VFP2 : RegisterClass<"ARM", [f64, v2i32, v2f32], 64,
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[D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15]> {
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let SubRegClassList = [SPR, SPR];
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}
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// Subset of DPR which can be used as a source of NEON scalars for 16-bit
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// operations
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def DPR_8 : RegisterClass<"ARM", [f64, v4i16, v2f32], 64,
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[D0, D1, D2, D3, D4, D5, D6, D7]> {
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let SubRegClassList = [SPR_8, SPR_8];
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}
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// Generic 128-bit vector register class.
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def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
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let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
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DPR, DPR];
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}
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// Subset of QPR that have 32-bit SPR subregs.
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def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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128,
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
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let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
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}
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// Condition code registers.
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def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
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//===----------------------------------------------------------------------===//
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// Subregister Set Definitions... now that we have all of the pieces, define the
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// sub registers for each register.
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//
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def arm_ssubreg_0 : PatLeaf<(i32 1)>;
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def arm_ssubreg_1 : PatLeaf<(i32 2)>;
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def arm_ssubreg_2 : PatLeaf<(i32 3)>;
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def arm_ssubreg_3 : PatLeaf<(i32 4)>;
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def arm_dsubreg_0 : PatLeaf<(i32 5)>;
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def arm_dsubreg_1 : PatLeaf<(i32 6)>;
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// S sub-registers of D registers.
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def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15],
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[S0, S2, S4, S6, S8, S10, S12, S14,
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S16, S18, S20, S22, S24, S26, S28, S30]>;
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def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15],
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[S1, S3, S5, S7, S9, S11, S13, S15,
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S17, S19, S21, S23, S25, S27, S29, S31]>;
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// S sub-registers of Q registers.
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def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
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[S0, S4, S8, S12, S16, S20, S24, S28]>;
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def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
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[S1, S5, S9, S13, S17, S21, S25, S29]>;
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def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
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[S2, S6, S10, S14, S18, S22, S26, S30]>;
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def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
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[S3, S7, S11, S15, S19, S23, S27, S31]>;
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// D sub-registers of Q registers.
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def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
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[D0, D2, D4, D6, D8, D10, D12, D14,
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D16, D18, D20, D22, D24, D26, D28, D30]>;
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def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
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[D1, D3, D5, D7, D9, D11, D13, D15,
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D17, D19, D21, D23, D25, D27, D29, D31]>;
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