Richard Sandiford 4c925c60eb [SystemZ] Use interlocked-access 1 instructions for CodeGen ... ...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197985 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-24 15:18:04 +00:00
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AArch64	[AArch64]Add patterns to match normal shift nodes: shl, sra and srl.	2013-12-24 09:00:21 +00:00
ARM	Unbreak ARM buildbots after r197653 by forcing the target triple on this test.	2013-12-19 18:14:42 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic
Hexagon
Inputs
Mips	Fix a problem with mips16 stubs when calls are transformed during	2013-12-18 23:57:48 +00:00
MSP430
NVPTX
PowerPC	Implement initial-exec TLS for PPC32.	2013-12-20 18:08:54 +00:00
R600	R600: Allow ftrunc	2013-12-20 05:11:55 +00:00
SPARC
SystemZ	[SystemZ] Use interlocked-access 1 instructions for CodeGen	2013-12-24 15:18:04 +00:00
Thumb
Thumb2
X86	AVX-512: fixed some patterns for MVT::i1	2013-12-24 14:24:07 +00:00
XCore