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Add a new DenseMapInfo::isEqual method to allow clients to redefine the equality predicate used when probing the hash table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42042 91177308-0d34-0410-b5e6-96231b3b80d8
895 lines
34 KiB
C++
895 lines
34 KiB
C++
//===- RegAllocBigBlock.cpp - A register allocator for large basic blocks -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RABigBlock class
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//
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//===----------------------------------------------------------------------===//
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// This register allocator is derived from RegAllocLocal.cpp. Like it, this
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// allocator works on one basic block at a time, oblivious to others.
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// However, the algorithm used here is suited for long blocks of
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// instructions - registers are spilled by greedily choosing those holding
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// values that will not be needed for the longest amount of time. This works
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// particularly well for blocks with 10 or more times as many instructions
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// as machine registers, but can be used for general code.
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//
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//===----------------------------------------------------------------------===//
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//
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// TODO: - automagically invoke linearscan for (groups of) small BBs?
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// - break ties when picking regs? (probably not worth it in a
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// JIT context)
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/BasicBlock.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
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namespace {
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static RegisterRegAlloc
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bigBlockRegAlloc("bigblock", " Big-block register allocator",
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createBigBlockRegisterAllocator);
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/// VRegKeyInfo - Defines magic values required to use VirtRegs as DenseMap
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/// keys.
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struct VRegKeyInfo {
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static inline unsigned getEmptyKey() { return -1U; }
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static inline unsigned getTombstoneKey() { return -2U; }
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static bool isEqual(unsigned LHS, unsigned RHS) { return LHS == RHS; }
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static unsigned getHashValue(const unsigned &Key) { return Key; }
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};
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/// This register allocator is derived from RegAllocLocal.cpp. Like it, this
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/// allocator works on one basic block at a time, oblivious to others.
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/// However, the algorithm used here is suited for long blocks of
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/// instructions - registers are spilled by greedily choosing those holding
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/// values that will not be needed for the longest amount of time. This works
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/// particularly well for blocks with 10 or more times as many instructions
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/// as machine registers, but can be used for general code.
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///
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/// TODO: - automagically invoke linearscan for (groups of) small BBs?
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/// - break ties when picking regs? (probably not worth it in a
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/// JIT context)
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///
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class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
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public:
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static char ID;
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RABigBlock() : MachineFunctionPass((intptr_t)&ID) {}
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private:
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/// TM - For getting at TargetMachine info
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///
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const TargetMachine *TM;
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/// MF - Our generic MachineFunction pointer
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///
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MachineFunction *MF;
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/// RegInfo - For dealing with machine register info (aliases, folds
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/// etc)
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const MRegisterInfo *RegInfo;
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/// LV - Our generic LiveVariables pointer
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///
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LiveVariables *LV;
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typedef SmallVector<unsigned, 2> VRegTimes;
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/// VRegReadTable - maps VRegs in a BB to the set of times they are read
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///
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DenseMap<unsigned, VRegTimes*, VRegKeyInfo> VRegReadTable;
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/// VRegReadIdx - keeps track of the "current time" in terms of
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/// positions in VRegReadTable
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DenseMap<unsigned, unsigned , VRegKeyInfo> VRegReadIdx;
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/// StackSlotForVirtReg - Maps virtual regs to the frame index where these
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/// values are spilled.
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IndexedMap<unsigned, VirtReg2IndexFunctor> StackSlotForVirtReg;
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/// Virt2PhysRegMap - This map contains entries for each virtual register
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/// that is currently available in a physical register.
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IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
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/// PhysRegsUsed - This array is effectively a map, containing entries for
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/// each physical register that currently has a value (ie, it is in
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/// Virt2PhysRegMap). The value mapped to is the virtual register
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/// corresponding to the physical register (the inverse of the
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/// Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
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/// because it is used by a future instruction, and to -2 if it is not
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/// allocatable. If the entry for a physical register is -1, then the
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/// physical register is "not in the map".
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///
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std::vector<int> PhysRegsUsed;
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/// VirtRegModified - This bitset contains information about which virtual
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/// registers need to be spilled back to memory when their registers are
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/// scavenged. If a virtual register has simply been rematerialized, there
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/// is no reason to spill it to memory when we need the register back.
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///
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std::vector<int> VirtRegModified;
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/// MBBLastInsnTime - the number of the the last instruction in MBB
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///
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int MBBLastInsnTime;
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/// MBBCurTime - the number of the the instruction being currently processed
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///
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int MBBCurTime;
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unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
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return Virt2PhysRegMap[VirtReg];
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}
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unsigned &getVirt2StackSlot(unsigned VirtReg) {
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return StackSlotForVirtReg[VirtReg];
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}
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/// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset
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///
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void markVirtRegModified(unsigned Reg, bool Val = true) {
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assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
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Reg -= MRegisterInfo::FirstVirtualRegister;
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if (VirtRegModified.size() <= Reg)
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VirtRegModified.resize(Reg+1);
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VirtRegModified[Reg] = Val;
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}
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/// isVirtRegModified - Lets us query the VirtRegModified bitset
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///
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bool isVirtRegModified(unsigned Reg) const {
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assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
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assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
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&& "Illegal virtual register!");
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return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
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}
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public:
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/// getPassName - returns the BigBlock allocator's name
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///
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virtual const char *getPassName() const {
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return "BigBlock Register Allocator";
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}
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/// getAnalaysisUsage - declares the required analyses
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///
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool runOnMachineFunction(MachineFunction &Fn);
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/// AllocateBasicBlock - Register allocate the specified basic block.
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///
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void AllocateBasicBlock(MachineBasicBlock &MBB);
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/// FillVRegReadTable - Fill out the table of vreg read times given a BB
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///
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void FillVRegReadTable(MachineBasicBlock &MBB);
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/// areRegsEqual - This method returns true if the specified registers are
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/// related to each other. To do this, it checks to see if they are equal
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/// or if the first register is in the alias set of the second register.
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///
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bool areRegsEqual(unsigned R1, unsigned R2) const {
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if (R1 == R2) return true;
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for (const unsigned *AliasSet = RegInfo->getAliasSet(R2);
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*AliasSet; ++AliasSet) {
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if (*AliasSet == R1) return true;
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}
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return false;
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}
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/// getStackSpaceFor - This returns the frame index of the specified virtual
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/// register on the stack, allocating space if necessary.
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int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
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/// removePhysReg - This method marks the specified physical register as no
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/// longer being in use.
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///
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void removePhysReg(unsigned PhysReg);
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/// spillVirtReg - This method spills the value specified by PhysReg into
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/// the virtual register slot specified by VirtReg. It then updates the RA
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/// data structures to indicate the fact that PhysReg is now available.
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///
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void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned VirtReg, unsigned PhysReg);
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/// spillPhysReg - This method spills the specified physical register into
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/// the virtual register slot associated with it. If OnlyVirtRegs is set to
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/// true, then the request is ignored if the physical register does not
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/// contain a virtual register.
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///
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void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
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unsigned PhysReg, bool OnlyVirtRegs = false);
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/// assignVirtToPhysReg - This method updates local state so that we know
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/// that PhysReg is the proper container for VirtReg now. The physical
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/// register must not be used for anything else when this is called.
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///
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void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
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/// isPhysRegAvailable - Return true if the specified physical register is
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/// free and available for use. This also includes checking to see if
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/// aliased registers are all free...
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///
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bool isPhysRegAvailable(unsigned PhysReg) const;
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/// getFreeReg - Look to see if there is a free register available in the
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/// specified register class. If not, return 0.
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///
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unsigned getFreeReg(const TargetRegisterClass *RC);
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/// chooseReg - Pick a physical register to hold the specified
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/// virtual register by choosing the one which will be read furthest
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/// in the future.
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///
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unsigned chooseReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg);
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/// reloadVirtReg - This method transforms the specified specified virtual
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/// register use to refer to a physical register. This method may do this
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/// in one of several ways: if the register is available in a physical
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/// register already, it uses that physical register. If the value is not
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/// in a physical register, and if there are physical registers available,
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/// it loads it into a register. If register pressure is high, and it is
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/// possible, it tries to fold the load of the virtual register into the
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/// instruction itself. It avoids doing this if register pressure is low to
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/// improve the chance that subsequent instructions can use the reloaded
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/// value. This method returns the modified instruction.
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///
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MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum);
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};
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char RABigBlock::ID = 0;
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}
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/// getStackSpaceFor - This allocates space for the specified virtual register
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/// to be held on the stack.
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int RABigBlock::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
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// Find the location Reg would belong...
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int FrameIdx = getVirt2StackSlot(VirtReg);
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if (FrameIdx)
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return FrameIdx - 1; // Already has space allocated?
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// Allocate a new stack object for this spill location...
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FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment());
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// Assign the slot...
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getVirt2StackSlot(VirtReg) = FrameIdx + 1;
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return FrameIdx;
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}
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/// removePhysReg - This method marks the specified physical register as no
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/// longer being in use.
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///
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void RABigBlock::removePhysReg(unsigned PhysReg) {
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PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
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}
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/// spillVirtReg - This method spills the value specified by PhysReg into the
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/// virtual register slot specified by VirtReg. It then updates the RA data
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/// structures to indicate the fact that PhysReg is now available.
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///
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void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned VirtReg, unsigned PhysReg) {
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assert(VirtReg && "Spilling a physical register is illegal!"
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" Must not have appropriate kill for the register or use exists beyond"
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" the intended one.");
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DOUT << " Spilling register " << RegInfo->getName(PhysReg)
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<< " containing %reg" << VirtReg;
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if (!isVirtRegModified(VirtReg))
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DOUT << " which has not been modified, so no store necessary!";
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// Otherwise, there is a virtual register corresponding to this physical
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// register. We only need to spill it into its stack slot if it has been
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// modified.
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if (isVirtRegModified(VirtReg)) {
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const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DOUT << " to stack slot #" << FrameIndex;
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RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
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++NumStores; // Update statistics
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}
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getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
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DOUT << "\n";
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removePhysReg(PhysReg);
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}
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/// spillPhysReg - This method spills the specified physical register into the
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/// virtual register slot associated with it. If OnlyVirtRegs is set to true,
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/// then the request is ignored if the physical register does not contain a
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/// virtual register.
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///
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void RABigBlock::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
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unsigned PhysReg, bool OnlyVirtRegs) {
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if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
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assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
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if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
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spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
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} else {
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// If the selected register aliases any other registers, we must make
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// sure that one of the aliases isn't alive.
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for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
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*AliasSet; ++AliasSet)
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if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
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PhysRegsUsed[*AliasSet] != -2) // If allocatable.
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if (PhysRegsUsed[*AliasSet])
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spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
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}
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}
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/// assignVirtToPhysReg - This method updates local state so that we know
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/// that PhysReg is the proper container for VirtReg now. The physical
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/// register must not be used for anything else when this is called.
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///
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void RABigBlock::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
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assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
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// Update information to note the fact that this register was just used, and
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// it holds VirtReg.
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PhysRegsUsed[PhysReg] = VirtReg;
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getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
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}
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/// isPhysRegAvailable - Return true if the specified physical register is free
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/// and available for use. This also includes checking to see if aliased
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/// registers are all free...
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///
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bool RABigBlock::isPhysRegAvailable(unsigned PhysReg) const {
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if (PhysRegsUsed[PhysReg] != -1) return false;
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// If the selected register aliases any other allocated registers, it is
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// not free!
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for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
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*AliasSet; ++AliasSet)
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if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use?
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return false; // Can't use this reg then.
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return true;
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}
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/// getFreeReg - Look to see if there is a free register available in the
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/// specified register class. If not, return 0.
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///
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unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) {
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// Get iterators defining the range of registers that are valid to allocate in
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// this class, which also specifies the preferred allocation order.
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TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
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TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
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for (; RI != RE; ++RI)
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if (isPhysRegAvailable(*RI)) { // Is reg unused?
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assert(*RI != 0 && "Cannot use register!");
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return *RI; // Found an unused register!
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}
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return 0;
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}
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/// chooseReg - Pick a physical register to hold the specified
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/// virtual register by choosing the one whose value will be read
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/// furthest in the future.
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///
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unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
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unsigned VirtReg) {
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const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
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// First check to see if we have a free register of the requested type...
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unsigned PhysReg = getFreeReg(RC);
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// If we didn't find an unused register, find the one which will be
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// read at the most distant point in time.
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if (PhysReg == 0) {
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unsigned delay=0, longest_delay=0;
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VRegTimes* ReadTimes;
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unsigned curTime = MBBCurTime;
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// for all physical regs in the RC,
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for(TargetRegisterClass::iterator pReg = RC->begin();
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pReg != RC->end(); ++pReg) {
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// how long until they're read?
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if(PhysRegsUsed[*pReg]>0) { // ignore non-allocatable regs
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ReadTimes = VRegReadTable[PhysRegsUsed[*pReg]];
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if(ReadTimes && !ReadTimes->empty()) {
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unsigned& pt = VRegReadIdx[PhysRegsUsed[*pReg]];
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while(pt < ReadTimes->size() && (*ReadTimes)[pt] < curTime) {
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++pt;
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}
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if(pt < ReadTimes->size())
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delay = (*ReadTimes)[pt] - curTime;
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else
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delay = MBBLastInsnTime + 1 - curTime;
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} else {
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// This register is only defined, but never
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// read in this MBB. Therefore the next read
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// happens after the end of this MBB
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delay = MBBLastInsnTime + 1 - curTime;
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}
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if(delay > longest_delay) {
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longest_delay = delay;
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PhysReg = *pReg;
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}
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}
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}
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if(PhysReg == 0) { // ok, now we're desperate. We couldn't choose
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// a register to spill by looking through the
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// read timetable, so now we just spill the
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// first allocatable register we find.
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// for all physical regs in the RC,
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for(TargetRegisterClass::iterator pReg = RC->begin();
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pReg != RC->end(); ++pReg) {
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// if we find a register we can spill
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if(PhysRegsUsed[*pReg]>=-1)
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PhysReg = *pReg; // choose it to be spilled
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}
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}
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|
|
assert(PhysReg && "couldn't choose a register to spill :( ");
|
|
// TODO: assert that RC->contains(PhysReg) / handle aliased registers?
|
|
|
|
// since we needed to look in the table we need to spill this register.
|
|
spillPhysReg(MBB, I, PhysReg);
|
|
}
|
|
|
|
// assign the vreg to our chosen physical register
|
|
assignVirtToPhysReg(VirtReg, PhysReg);
|
|
return PhysReg; // and return it
|
|
}
|
|
|
|
|
|
/// reloadVirtReg - This method transforms an instruction with a virtual
|
|
/// register use to one that references a physical register. It does this as
|
|
/// follows:
|
|
///
|
|
/// 1) If the register is already in a physical register, it uses it.
|
|
/// 2) Otherwise, if there is a free physical register, it uses that.
|
|
/// 3) Otherwise, it calls chooseReg() to get the physical register
|
|
/// holding the most distantly needed value, generating a spill in
|
|
/// the process.
|
|
///
|
|
/// This method returns the modified instruction.
|
|
MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
|
|
unsigned OpNum) {
|
|
unsigned VirtReg = MI->getOperand(OpNum).getReg();
|
|
|
|
// If the virtual register is already available in a physical register,
|
|
// just update the instruction and return.
|
|
if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
|
|
MI->getOperand(OpNum).setReg(PR);
|
|
return MI;
|
|
}
|
|
|
|
// Otherwise, if we have free physical registers available to hold the
|
|
// value, use them.
|
|
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
|
|
unsigned PhysReg = getFreeReg(RC);
|
|
int FrameIndex = getStackSpaceFor(VirtReg, RC);
|
|
|
|
if (PhysReg) { // we have a free register, so use it.
|
|
assignVirtToPhysReg(VirtReg, PhysReg);
|
|
} else { // no free registers available.
|
|
// try to fold the spill into the instruction
|
|
if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, OpNum, FrameIndex)) {
|
|
++NumFolded;
|
|
// Since we changed the address of MI, make sure to update live variables
|
|
// to know that the new instruction has the properties of the old one.
|
|
LV->instructionChanged(MI, FMI);
|
|
return MBB.insert(MBB.erase(MI), FMI);
|
|
}
|
|
|
|
// determine which of the physical registers we'll kill off, since we
|
|
// couldn't fold.
|
|
PhysReg = chooseReg(MBB, MI, VirtReg);
|
|
}
|
|
|
|
// this virtual register is now unmodified (since we just reloaded it)
|
|
markVirtRegModified(VirtReg, false);
|
|
|
|
DOUT << " Reloading %reg" << VirtReg << " into "
|
|
<< RegInfo->getName(PhysReg) << "\n";
|
|
|
|
// Add move instruction(s)
|
|
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
|
|
++NumLoads; // Update statistics
|
|
|
|
MF->setPhysRegUsed(PhysReg);
|
|
MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
|
|
return MI;
|
|
}
|
|
|
|
/// Fill out the vreg read timetable. Since ReadTime increases
|
|
/// monotonically, the individual readtime sets will be sorted
|
|
/// in ascending order.
|
|
void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) {
|
|
// loop over each instruction
|
|
MachineBasicBlock::iterator MII;
|
|
unsigned ReadTime;
|
|
|
|
for(ReadTime=0, MII = MBB.begin(); MII != MBB.end(); ++ReadTime, ++MII) {
|
|
MachineInstr *MI = MII;
|
|
|
|
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
// look for vreg reads..
|
|
if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
|
|
MRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
// ..and add them to the read table.
|
|
VRegTimes* &Times = VRegReadTable[MO.getReg()];
|
|
if(!VRegReadTable[MO.getReg()]) {
|
|
Times = new VRegTimes;
|
|
VRegReadIdx[MO.getReg()] = 0;
|
|
}
|
|
Times->push_back(ReadTime);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
MBBLastInsnTime = ReadTime;
|
|
|
|
for(DenseMap<unsigned, VRegTimes*, VRegKeyInfo>::iterator Reads = VRegReadTable.begin();
|
|
Reads != VRegReadTable.end(); ++Reads) {
|
|
if(Reads->second) {
|
|
DOUT << "Reads[" << Reads->first << "]=" << Reads->second->size() << "\n";
|
|
}
|
|
}
|
|
}
|
|
|
|
/// isReadModWriteImplicitKill - True if this is an implicit kill for a
|
|
/// read/mod/write register, i.e. update partial register.
|
|
static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
|
|
MO.isDef() && !MO.isDead())
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// isReadModWriteImplicitDef - True if this is an implicit def for a
|
|
/// read/mod/write register, i.e. update partial register.
|
|
static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
|
|
!MO.isDef() && MO.isKill())
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
|
|
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|
// loop over each instruction
|
|
MachineBasicBlock::iterator MII = MBB.begin();
|
|
const TargetInstrInfo &TII = *TM->getInstrInfo();
|
|
|
|
DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
|
|
if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
|
|
|
|
// If this is the first basic block in the machine function, add live-in
|
|
// registers as active.
|
|
if (&MBB == &*MF->begin()) {
|
|
for (MachineFunction::livein_iterator I = MF->livein_begin(),
|
|
E = MF->livein_end(); I != E; ++I) {
|
|
unsigned Reg = I->first;
|
|
MF->setPhysRegUsed(Reg);
|
|
PhysRegsUsed[Reg] = 0; // It is free and reserved now
|
|
for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
|
|
*AliasSet; ++AliasSet) {
|
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
|
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
|
|
MF->setPhysRegUsed(*AliasSet);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Otherwise, sequentially allocate each instruction in the MBB.
|
|
MBBCurTime = -1;
|
|
while (MII != MBB.end()) {
|
|
MachineInstr *MI = MII++;
|
|
MBBCurTime++;
|
|
const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
|
|
DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
|
|
DOUT << " Regs have values: ";
|
|
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
|
|
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
|
|
DOUT << "[" << RegInfo->getName(i)
|
|
<< ",%reg" << PhysRegsUsed[i] << "] ";
|
|
DOUT << "\n");
|
|
|
|
SmallVector<unsigned, 8> Kills;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isKill()) {
|
|
if (!MO.isImplicit())
|
|
Kills.push_back(MO.getReg());
|
|
else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
|
|
// These are extra physical register kills when a sub-register
|
|
// is defined (def of a sub-register is a read/mod/write of the
|
|
// larger registers). Ignore.
|
|
Kills.push_back(MO.getReg());
|
|
}
|
|
}
|
|
|
|
// Get the used operands into registers. This has the potential to spill
|
|
// incoming values if we are out of registers. Note that we completely
|
|
// ignore physical register uses here. We assume that if an explicit
|
|
// physical register is referenced by the instruction, that it is guaranteed
|
|
// to be live-in, or the input is badly hosed.
|
|
//
|
|
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
// here we are looking for only used operands (never def&use)
|
|
if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
|
|
MRegisterInfo::isVirtualRegister(MO.getReg()))
|
|
MI = reloadVirtReg(MBB, MI, i);
|
|
}
|
|
|
|
// If this instruction is the last user of this register, kill the
|
|
// value, freeing the register being used, so it doesn't need to be
|
|
// spilled to memory.
|
|
//
|
|
for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
|
|
unsigned VirtReg = Kills[i];
|
|
unsigned PhysReg = VirtReg;
|
|
if (MRegisterInfo::isVirtualRegister(VirtReg)) {
|
|
// If the virtual register was never materialized into a register, it
|
|
// might not be in the map, but it won't hurt to zero it out anyway.
|
|
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
|
|
PhysReg = PhysRegSlot;
|
|
PhysRegSlot = 0;
|
|
} else if (PhysRegsUsed[PhysReg] == -2) {
|
|
// Unallocatable register dead, ignore.
|
|
continue;
|
|
} else {
|
|
assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1 &&
|
|
"Silently clearing a virtual register?");
|
|
}
|
|
|
|
if (PhysReg) {
|
|
DOUT << " Last use of " << RegInfo->getName(PhysReg)
|
|
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
|
removePhysReg(PhysReg);
|
|
for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
|
|
*AliasSet; ++AliasSet) {
|
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
|
DOUT << " Last use of "
|
|
<< RegInfo->getName(*AliasSet)
|
|
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
|
removePhysReg(*AliasSet);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Loop over all of the operands of the instruction, spilling registers that
|
|
// are defined, and marking explicit destinations in the PhysRegsUsed map.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
|
|
MRegisterInfo::isPhysicalRegister(MO.getReg())) {
|
|
unsigned Reg = MO.getReg();
|
|
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
|
|
// These are extra physical register defs when a sub-register
|
|
// is defined (def of a sub-register is a read/mod/write of the
|
|
// larger registers). Ignore.
|
|
if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
|
|
|
|
MF->setPhysRegUsed(Reg);
|
|
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
|
|
PhysRegsUsed[Reg] = 0; // It is free and reserved now
|
|
for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
|
|
*AliasSet; ++AliasSet) {
|
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
|
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
|
|
MF->setPhysRegUsed(*AliasSet);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Loop over the implicit defs, spilling them as well.
|
|
if (TID.ImplicitDefs) {
|
|
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
|
|
*ImplicitDefs; ++ImplicitDefs) {
|
|
unsigned Reg = *ImplicitDefs;
|
|
if (PhysRegsUsed[Reg] != -2) {
|
|
spillPhysReg(MBB, MI, Reg, true);
|
|
PhysRegsUsed[Reg] = 0; // It is free and reserved now
|
|
}
|
|
MF->setPhysRegUsed(Reg);
|
|
for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
|
|
*AliasSet; ++AliasSet) {
|
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
|
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
|
|
MF->setPhysRegUsed(*AliasSet);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
SmallVector<unsigned, 8> DeadDefs;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isDead())
|
|
DeadDefs.push_back(MO.getReg());
|
|
}
|
|
|
|
// Okay, we have allocated all of the source operands and spilled any values
|
|
// that would be destroyed by defs of this instruction. Loop over the
|
|
// explicit defs and assign them to a register, spilling incoming values if
|
|
// we need to scavenge a register.
|
|
//
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand& MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isDef() && MO.getReg() &&
|
|
MRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
unsigned DestVirtReg = MO.getReg();
|
|
unsigned DestPhysReg;
|
|
|
|
// If DestVirtReg already has a value, use it.
|
|
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
|
|
DestPhysReg = chooseReg(MBB, MI, DestVirtReg);
|
|
MF->setPhysRegUsed(DestPhysReg);
|
|
markVirtRegModified(DestVirtReg);
|
|
MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
|
|
}
|
|
}
|
|
|
|
// If this instruction defines any registers that are immediately dead,
|
|
// kill them now.
|
|
//
|
|
for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
|
|
unsigned VirtReg = DeadDefs[i];
|
|
unsigned PhysReg = VirtReg;
|
|
if (MRegisterInfo::isVirtualRegister(VirtReg)) {
|
|
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
|
|
PhysReg = PhysRegSlot;
|
|
assert(PhysReg != 0);
|
|
PhysRegSlot = 0;
|
|
} else if (PhysRegsUsed[PhysReg] == -2) {
|
|
// Unallocatable register dead, ignore.
|
|
continue;
|
|
}
|
|
|
|
if (PhysReg) {
|
|
DOUT << " Register " << RegInfo->getName(PhysReg)
|
|
<< " [%reg" << VirtReg
|
|
<< "] is never used, removing it frame live list\n";
|
|
removePhysReg(PhysReg);
|
|
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
|
|
*AliasSet; ++AliasSet) {
|
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
|
DOUT << " Register " << RegInfo->getName(*AliasSet)
|
|
<< " [%reg" << *AliasSet
|
|
<< "] is never used, removing it frame live list\n";
|
|
removePhysReg(*AliasSet);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Finally, if this is a noop copy instruction, zap it.
|
|
unsigned SrcReg, DstReg;
|
|
if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) {
|
|
LV->removeVirtualRegistersKilled(MI);
|
|
LV->removeVirtualRegistersDead(MI);
|
|
MBB.erase(MI);
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
|
|
|
|
// Spill all physical registers holding virtual registers now.
|
|
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
|
|
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
|
|
if (unsigned VirtReg = PhysRegsUsed[i])
|
|
spillVirtReg(MBB, MI, VirtReg, i);
|
|
else
|
|
removePhysReg(i);
|
|
}
|
|
|
|
/// runOnMachineFunction - Register allocate the whole function
|
|
///
|
|
bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) {
|
|
DOUT << "Machine Function " << "\n";
|
|
MF = &Fn;
|
|
TM = &Fn.getTarget();
|
|
RegInfo = TM->getRegisterInfo();
|
|
LV = &getAnalysis<LiveVariables>();
|
|
|
|
PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
|
|
|
|
// At various places we want to efficiently check to see whether a register
|
|
// is allocatable. To handle this, we mark all unallocatable registers as
|
|
// being pinned down, permanently.
|
|
{
|
|
BitVector Allocable = RegInfo->getAllocatableSet(Fn);
|
|
for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
|
|
if (!Allocable[i])
|
|
PhysRegsUsed[i] = -2; // Mark the reg unallocable.
|
|
}
|
|
|
|
// initialize the virtual->physical register map to have a 'null'
|
|
// mapping for all virtual registers
|
|
Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg());
|
|
StackSlotForVirtReg.grow(MF->getSSARegMap()->getLastVirtReg());
|
|
VirtRegModified.resize(MF->getSSARegMap()->getLastVirtReg() - MRegisterInfo::FirstVirtualRegister + 1,0);
|
|
|
|
// Loop over all of the basic blocks, eliminating virtual register references
|
|
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
|
|
MBB != MBBe; ++MBB) {
|
|
// fill out the read timetable
|
|
FillVRegReadTable(*MBB);
|
|
// use it to allocate the BB
|
|
AllocateBasicBlock(*MBB);
|
|
// clear it
|
|
VRegReadTable.clear();
|
|
}
|
|
|
|
StackSlotForVirtReg.clear();
|
|
PhysRegsUsed.clear();
|
|
VirtRegModified.clear();
|
|
Virt2PhysRegMap.clear();
|
|
return true;
|
|
}
|
|
|
|
FunctionPass *llvm::createBigBlockRegisterAllocator() {
|
|
return new RABigBlock();
|
|
}
|
|
|