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f35ce2376c
The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208289 91177308-0d34-0410-b5e6-96231b3b80d8
265 lines
8.6 KiB
TableGen
265 lines
8.6 KiB
TableGen
//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Haswell to support instruction
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// scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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def HaswellModel : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and HW can decode 4
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// instructions per cycle.
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let IssueWidth = 4;
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let MicroOpBufferSize = 192; // Based on the reorder buffer.
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let LoadLatency = 4;
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let MispredictPenalty = 16;
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// Based on the LSD (loop-stream detector) queue size and benchmarking data.
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let LoopMicroOpBufferSize = 50;
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// FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
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// the scheduler to assign a default model to unrecognized opcodes.
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let CompleteModel = 0;
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}
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let SchedModel = HaswellModel in {
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// Haswell can issue micro-ops to 8 different ports in one cycle.
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// Ports 0, 1, 5, and 6 handle all computation.
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// Port 4 gets the data half of stores. Store data can be available later than
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// the store address, but since we don't model the latency of stores, we can
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// ignore that.
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// Ports 2 and 3 are identical. They handle loads and the address half of
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// stores. Port 7 can handle address calculations.
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def HWPort0 : ProcResource<1>;
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def HWPort1 : ProcResource<1>;
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def HWPort2 : ProcResource<1>;
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def HWPort3 : ProcResource<1>;
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def HWPort4 : ProcResource<1>;
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def HWPort5 : ProcResource<1>;
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def HWPort6 : ProcResource<1>;
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def HWPort7 : ProcResource<1>;
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// Many micro-ops are capable of issuing on multiple ports.
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def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
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def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
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def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
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def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
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def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
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def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
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def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
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def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
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// 60 Entry Unified Scheduler
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def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
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HWPort5, HWPort6, HWPort7]> {
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let BufferSize=60;
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}
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// Integer division issued on port 0.
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def HWDivider : ProcResource<1>;
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// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 4>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when queued in the reservation station.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
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ProcResourceKind ExePort,
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int Lat> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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// Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
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let Latency = !add(Lat, 4);
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}
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}
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// A folded store needs a cycle on port 4 for the store data, but it does not
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// need an extra port 2/3 cycle to recompute the address.
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def : WriteRes<WriteRMW, [HWPort4]>;
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// Store_addr on 237.
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// Store_data on 4.
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def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
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def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
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def : WriteRes<WriteMove, [HWPort0156]>;
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def : WriteRes<WriteZero, []>;
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defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
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defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
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def : WriteRes<WriteIMulH, []> { let Latency = 3; }
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defm : HWWriteResPair<WriteShift, HWPort06, 1>;
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defm : HWWriteResPair<WriteJump, HWPort06, 1>;
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// This is for simple LEAs with one or two input operands.
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// The complex ones can only execute on port 1, and they require two cycles on
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// the port to read all inputs. We don't model that.
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def : WriteRes<WriteLEA, [HWPort15]>;
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// This is quite rough, latency depends on the dividend.
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def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
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let Latency = 25;
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let ResourceCycles = [1, 10];
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}
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def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
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let Latency = 29;
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let ResourceCycles = [1, 1, 10];
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}
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// Scalar and vector floating point.
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defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
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defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
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defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
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defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
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defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
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defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
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defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
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defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
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defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
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defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
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defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
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def : WriteRes<WriteFVarBlend, [HWPort5]> {
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let Latency = 2;
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let ResourceCycles = [2];
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}
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def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
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let Latency = 6;
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let ResourceCycles = [2, 1];
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}
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// Vector integer operations.
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defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
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defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
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defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
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defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
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defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
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defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
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defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
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def : WriteRes<WriteVarBlend, [HWPort5]> {
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let Latency = 2;
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let ResourceCycles = [2];
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}
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def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
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let Latency = 6;
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let ResourceCycles = [2, 1];
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}
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def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
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let Latency = 2;
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let ResourceCycles = [2, 1];
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}
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def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
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let Latency = 6;
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let ResourceCycles = [2, 1, 1];
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}
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def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
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let Latency = 6;
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let ResourceCycles = [1, 2];
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}
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def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
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let Latency = 6;
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let ResourceCycles = [1, 1, 2];
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}
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// String instructions.
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// Packed Compare Implicit Length Strings, Return Mask
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def : WriteRes<WritePCmpIStrM, [HWPort0]> {
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let Latency = 10;
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let ResourceCycles = [3];
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}
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def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
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let Latency = 10;
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let ResourceCycles = [3, 1];
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}
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// Packed Compare Explicit Length Strings, Return Mask
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def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
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let Latency = 10;
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let ResourceCycles = [3, 2, 4];
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}
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def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
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let Latency = 10;
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let ResourceCycles = [6, 2, 1];
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}
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// Packed Compare Implicit Length Strings, Return Index
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def : WriteRes<WritePCmpIStrI, [HWPort0]> {
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let Latency = 11;
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let ResourceCycles = [3];
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}
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def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
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let Latency = 11;
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let ResourceCycles = [3, 1];
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}
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// Packed Compare Explicit Length Strings, Return Index
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def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
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let Latency = 11;
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let ResourceCycles = [6, 2];
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}
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def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
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let Latency = 11;
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let ResourceCycles = [3, 2, 2, 1];
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}
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// AES Instructions.
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def : WriteRes<WriteAESDecEnc, [HWPort5]> {
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let Latency = 7;
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let ResourceCycles = [1];
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}
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def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
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let Latency = 7;
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let ResourceCycles = [1, 1];
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}
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def : WriteRes<WriteAESIMC, [HWPort5]> {
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let Latency = 14;
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let ResourceCycles = [2];
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}
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def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
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let Latency = 14;
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let ResourceCycles = [2, 1];
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}
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def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
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let Latency = 10;
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let ResourceCycles = [2, 8];
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}
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def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
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let Latency = 10;
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let ResourceCycles = [2, 7, 1];
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}
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// Carry-less multiplication instructions.
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def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
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let Latency = 7;
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let ResourceCycles = [2, 1];
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}
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def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
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let Latency = 7;
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let ResourceCycles = [2, 1, 1];
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}
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def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
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def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
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def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
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def : WriteRes<WriteNop, []>;
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} // SchedModel
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