llvm-6502/test
Evan Cheng c4b527ac06 DAGCombine's logic for forming pre- and post- indexed loads / stores were being
overly conservative. It was concerned about cases where it would prohibit
folding simple [r, c] addressing modes. e.g.
  ldr r0, [r2]
  ldr r1, [r2, #4]
=>
  ldr r0, [r2], #4
  ldr r1, [r2]
Change the logic to look for such cases which allows it to form indexed memory
ops more aggressively.

rdar://10674430


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 01:37:24 +00:00
..
Analysis
Archive
Assembler
Bindings/Ocaml
Bitcode
BugPoint
CodeGen DAGCombine's logic for forming pre- and post- indexed loads / stores were being 2012-01-13 01:37:24 +00:00
DebugInfo Don't avoid recursing for pointer types, just reference types. Expand on 2012-01-11 00:01:29 +00:00
ExecutionEngine
Feature
Instrumentation/AddressSanitizer
Integer
lib
Linker
MC Remove test case, as Chris suggested. 2012-01-12 19:54:02 +00:00
Object
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TableGen
Transforms Implement proper ObjC ARC objc_retainBlock "escape" analysis, so that 2012-01-13 00:39:07 +00:00
Unit
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CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
site.exp.in
TestRunner.sh