mirror of
https://github.com/c64scene-ar/llvm-6502.git
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This helps cases like 2008-07-19-movups-spills.ll, but doesn't have an obvious impact on benchmarks git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127347 91177308-0d34-0410-b5e6-96231b3b80d8
768 lines
27 KiB
C++
768 lines
27 KiB
C++
//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the ScheduleDAG class, which is a base class used by
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// scheduling implementation classes.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "SDNodeDbgValue.h"
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#include "ScheduleDAGSDNodes.h"
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#include "InstrEmitter.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(LoadsClustered, "Number of loads clustered together");
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// This allows latency based scheduler to notice high latency instructions
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// without a target itinerary. The choise if number here has more to do with
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// balancing scheduler heursitics than with the actual machine latency.
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static cl::opt<int> HighLatencyCycles(
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"sched-high-latency-cycles", cl::Hidden, cl::init(10),
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cl::desc("Roughly estimate the number of cycles that 'long latency'"
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"instructions take for targets with no itinerary"));
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ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
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: ScheduleDAG(mf),
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InstrItins(mf.getTarget().getInstrItineraryData()) {}
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/// Run - perform scheduling.
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///
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void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
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MachineBasicBlock::iterator insertPos) {
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DAG = dag;
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ScheduleDAG::Run(bb, insertPos);
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}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) {
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#ifndef NDEBUG
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const SUnit *Addr = 0;
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if (!SUnits.empty())
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Addr = &SUnits[0];
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#endif
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SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
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assert((Addr == 0 || Addr == &SUnits[0]) &&
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"SUnits std::vector reallocated on the fly!");
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SUnits.back().OrigNode = &SUnits.back();
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SUnit *SU = &SUnits.back();
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const TargetLowering &TLI = DAG->getTargetLoweringInfo();
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if (!N ||
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(N->isMachineOpcode() &&
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N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
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SU->SchedulingPref = Sched::None;
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else
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SU->SchedulingPref = TLI.getSchedulingPreference(N);
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return SU;
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}
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SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
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SUnit *SU = NewSUnit(Old->getNode());
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SU->OrigNode = Old->OrigNode;
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SU->Latency = Old->Latency;
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SU->isCall = Old->isCall;
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SU->isTwoAddress = Old->isTwoAddress;
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SU->isCommutable = Old->isCommutable;
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SU->hasPhysRegDefs = Old->hasPhysRegDefs;
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SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
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SU->SchedulingPref = Old->SchedulingPref;
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Old->isCloned = true;
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return SU;
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}
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/// CheckForPhysRegDependency - Check if the dependency between def and use of
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/// a specified operand is a physical register dependency. If so, returns the
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/// register and the cost of copying the register.
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static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
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const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII,
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unsigned &PhysReg, int &Cost) {
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if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
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return;
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return;
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unsigned ResNo = User->getOperand(2).getResNo();
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if (Def->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
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if (ResNo >= II.getNumDefs() &&
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II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
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PhysReg = Reg;
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const TargetRegisterClass *RC =
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TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
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Cost = RC->getCopyCost();
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}
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}
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}
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static void AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
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SmallVector<EVT, 4> VTs;
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SDNode *GlueDestNode = Glue.getNode();
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// Don't add glue from a node to itself.
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if (GlueDestNode == N) return;
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// Don't add glue to something which already has glue.
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if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return;
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for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
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VTs.push_back(N->getValueType(I));
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if (AddGlue)
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VTs.push_back(MVT::Glue);
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SmallVector<SDValue, 4> Ops;
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for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
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Ops.push_back(N->getOperand(I));
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if (GlueDestNode)
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Ops.push_back(Glue);
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SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size());
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MachineSDNode::mmo_iterator Begin = 0, End = 0;
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MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
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// Store memory references.
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if (MN) {
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Begin = MN->memoperands_begin();
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End = MN->memoperands_end();
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}
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DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size());
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// Reset the memory references
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if (MN)
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MN->setMemRefs(Begin, End);
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}
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/// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
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/// This function finds loads of the same base and different offsets. If the
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/// offsets are not far apart (target specific), it add MVT::Glue inputs and
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/// outputs to ensure they are scheduled together and in order. This
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/// optimization may benefit some targets by improving cache locality.
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void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
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SDNode *Chain = 0;
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unsigned NumOps = Node->getNumOperands();
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if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
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Chain = Node->getOperand(NumOps-1).getNode();
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if (!Chain)
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return;
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// Look for other loads of the same chain. Find loads that are loading from
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// the same base pointer and different offsets.
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SmallPtrSet<SDNode*, 16> Visited;
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SmallVector<int64_t, 4> Offsets;
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DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
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bool Cluster = false;
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SDNode *Base = Node;
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for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
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I != E; ++I) {
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SDNode *User = *I;
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if (User == Node || !Visited.insert(User))
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continue;
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int64_t Offset1, Offset2;
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if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
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Offset1 == Offset2)
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// FIXME: Should be ok if they addresses are identical. But earlier
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// optimizations really should have eliminated one of the loads.
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continue;
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if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
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Offsets.push_back(Offset1);
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O2SMap.insert(std::make_pair(Offset2, User));
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Offsets.push_back(Offset2);
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if (Offset2 < Offset1)
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Base = User;
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Cluster = true;
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}
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if (!Cluster)
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return;
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// Sort them in increasing order.
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std::sort(Offsets.begin(), Offsets.end());
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// Check if the loads are close enough.
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SmallVector<SDNode*, 4> Loads;
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unsigned NumLoads = 0;
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int64_t BaseOff = Offsets[0];
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SDNode *BaseLoad = O2SMap[BaseOff];
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Loads.push_back(BaseLoad);
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for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
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int64_t Offset = Offsets[i];
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SDNode *Load = O2SMap[Offset];
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if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
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break; // Stop right here. Ignore loads that are further away.
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Loads.push_back(Load);
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++NumLoads;
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}
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if (NumLoads == 0)
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return;
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// Cluster loads by adding MVT::Glue outputs and inputs. This also
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// ensure they are scheduled in order of increasing addresses.
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SDNode *Lead = Loads[0];
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AddGlue(Lead, SDValue(0, 0), true, DAG);
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SDValue InGlue = SDValue(Lead, Lead->getNumValues() - 1);
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for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
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bool OutGlue = I < E - 1;
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SDNode *Load = Loads[I];
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AddGlue(Load, InGlue, OutGlue, DAG);
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if (OutGlue)
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InGlue = SDValue(Load, Load->getNumValues() - 1);
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++LoadsClustered;
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}
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}
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/// ClusterNodes - Cluster certain nodes which should be scheduled together.
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///
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void ScheduleDAGSDNodes::ClusterNodes() {
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI) {
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SDNode *Node = &*NI;
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if (!Node || !Node->isMachineOpcode())
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continue;
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unsigned Opc = Node->getMachineOpcode();
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const TargetInstrDesc &TID = TII->get(Opc);
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if (TID.mayLoad())
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// Cluster loads from "near" addresses into combined SUnits.
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ClusterNeighboringLoads(Node);
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}
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}
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void ScheduleDAGSDNodes::BuildSchedUnits() {
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// During scheduling, the NodeId field of SDNode is used to map SDNodes
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// to their associated SUnits by holding SUnits table indices. A value
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// of -1 means the SDNode does not yet have an associated SUnit.
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unsigned NumNodes = 0;
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI) {
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NI->setNodeId(-1);
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++NumNodes;
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}
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// Reserve entries in the vector for each of the SUnits we are creating. This
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// ensure that reallocation of the vector won't happen, so SUnit*'s won't get
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// invalidated.
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// FIXME: Multiply by 2 because we may clone nodes during scheduling.
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// This is a temporary workaround.
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SUnits.reserve(NumNodes * 2);
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// Add all nodes in depth first order.
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SmallVector<SDNode*, 64> Worklist;
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SmallPtrSet<SDNode*, 64> Visited;
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Worklist.push_back(DAG->getRoot().getNode());
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Visited.insert(DAG->getRoot().getNode());
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while (!Worklist.empty()) {
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SDNode *NI = Worklist.pop_back_val();
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// Add all operands to the worklist unless they've already been added.
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for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
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if (Visited.insert(NI->getOperand(i).getNode()))
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Worklist.push_back(NI->getOperand(i).getNode());
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if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
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continue;
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// If this node has already been processed, stop now.
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if (NI->getNodeId() != -1) continue;
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SUnit *NodeSUnit = NewSUnit(NI);
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// See if anything is glued to this node, if so, add them to glued
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// nodes. Nodes can have at most one glue input and one glue output. Glue
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// is required to be the last operand and result of a node.
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// Scan up to find glued preds.
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SDNode *N = NI;
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while (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
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N = N->getOperand(N->getNumOperands()-1).getNode();
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
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NodeSUnit->isCall = true;
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}
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// Scan down to find any glued succs.
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N = NI;
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while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
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SDValue GlueVal(N, N->getNumValues()-1);
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// There are either zero or one users of the Glue result.
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bool HasGlueUse = false;
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for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
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UI != E; ++UI)
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if (GlueVal.isOperandOf(*UI)) {
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HasGlueUse = true;
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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N = *UI;
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if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
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NodeSUnit->isCall = true;
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break;
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}
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if (!HasGlueUse) break;
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}
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// If there are glue operands involved, N is now the bottom-most node
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// of the sequence of nodes that are glued together.
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// Update the SUnit.
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NodeSUnit->setNode(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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// Compute NumRegDefsLeft. This must be done before AddSchedEdges.
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InitNumRegDefsLeft(NodeSUnit);
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// Assign the Latency field of NodeSUnit using target-provided information.
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ComputeLatency(NodeSUnit);
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}
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}
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void ScheduleDAGSDNodes::AddSchedEdges() {
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const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
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// Check to see if the scheduler cares about latencies.
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bool UnitLatencies = ForceUnitLatencies();
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// Pass 2: add the preds, succs, etc.
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
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SUnit *SU = &SUnits[su];
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SDNode *MainNode = SU->getNode();
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if (MainNode->isMachineOpcode()) {
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unsigned Opc = MainNode->getMachineOpcode();
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const TargetInstrDesc &TID = TII->get(Opc);
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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SU->isTwoAddress = true;
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break;
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}
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}
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if (TID.isCommutable())
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SU->isCommutable = true;
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}
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// Find all predecessors and successors of the group.
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for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
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if (N->isMachineOpcode() &&
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TII->get(N->getMachineOpcode()).getImplicitDefs()) {
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SU->hasPhysRegClobbers = true;
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unsigned NumUsed = InstrEmitter::CountResults(N);
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while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
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--NumUsed; // Skip over unused values at the end.
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if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
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SU->hasPhysRegDefs = true;
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}
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDNode *OpN = N->getOperand(i).getNode();
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if (isPassiveNode(OpN)) continue; // Not scheduled.
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SUnit *OpSU = &SUnits[OpN->getNodeId()];
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assert(OpSU && "Node has no SUnit!");
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if (OpSU == SU) continue; // In the same group.
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EVT OpVT = N->getOperand(i).getValueType();
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assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
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bool isChain = OpVT == MVT::Other;
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unsigned PhysReg = 0;
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int Cost = 1;
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// Determine if this is a physical register dependency.
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CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
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assert((PhysReg == 0 || !isChain) &&
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"Chain dependence via physreg data?");
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// FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
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// emits a copy from the physical register to a virtual register unless
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// it requires a cross class copy (cost < 0). That means we are only
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// treating "expensive to copy" register dependency as physical register
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// dependency. This may change in the future though.
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if (Cost >= 0)
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PhysReg = 0;
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// If this is a ctrl dep, latency is 1.
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unsigned OpLatency = isChain ? 1 : OpSU->Latency;
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const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
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OpLatency, PhysReg);
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if (!isChain && !UnitLatencies) {
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ComputeOperandLatency(OpN, N, i, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
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}
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if (!SU->addPred(dep) && !dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
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// Multiple register uses are combined in the same SUnit. For example,
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// we could have a set of glued nodes with all their defs consumed by
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// another set of glued nodes. Register pressure tracking sees this as
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// a single use, so to keep pressure balanced we reduce the defs.
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//
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// We can't tell (without more book-keeping) if this results from
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// glued nodes or duplicate operands. As long as we don't reduce
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// NumRegDefsLeft to zero, we handle the common cases well.
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--OpSU->NumRegDefsLeft;
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}
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}
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}
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}
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}
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/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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/// are input. This SUnit graph is similar to the SelectionDAG, but
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/// excludes nodes that aren't interesting to scheduling, and represents
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/// glued together nodes with a single SUnit.
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void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
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// Cluster certain nodes which should be scheduled together.
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ClusterNodes();
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// Populate the SUnits array.
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BuildSchedUnits();
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// Compute all the scheduling dependencies between nodes.
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AddSchedEdges();
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}
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// Initialize NumNodeDefs for the current Node's opcode.
|
|
void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
|
|
// Check for phys reg copy.
|
|
if (!Node)
|
|
return;
|
|
|
|
if (!Node->isMachineOpcode()) {
|
|
if (Node->getOpcode() == ISD::CopyFromReg)
|
|
NodeNumDefs = 1;
|
|
else
|
|
NodeNumDefs = 0;
|
|
return;
|
|
}
|
|
unsigned POpc = Node->getMachineOpcode();
|
|
if (POpc == TargetOpcode::IMPLICIT_DEF) {
|
|
// No register need be allocated for this.
|
|
NodeNumDefs = 0;
|
|
return;
|
|
}
|
|
unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
|
|
// Some instructions define regs that are not represented in the selection DAG
|
|
// (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
|
|
NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
|
|
DefIdx = 0;
|
|
}
|
|
|
|
// Construct a RegDefIter for this SUnit and find the first valid value.
|
|
ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
|
|
const ScheduleDAGSDNodes *SD)
|
|
: SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
|
|
InitNodeNumDefs();
|
|
Advance();
|
|
}
|
|
|
|
// Advance to the next valid value defined by the SUnit.
|
|
void ScheduleDAGSDNodes::RegDefIter::Advance() {
|
|
for (;Node;) { // Visit all glued nodes.
|
|
for (;DefIdx < NodeNumDefs; ++DefIdx) {
|
|
if (!Node->hasAnyUseOfValue(DefIdx))
|
|
continue;
|
|
if (Node->isMachineOpcode() &&
|
|
Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG) {
|
|
// Propagate the incoming (full-register) type. I doubt it's needed.
|
|
ValueType = Node->getOperand(0).getValueType();
|
|
}
|
|
else {
|
|
ValueType = Node->getValueType(DefIdx);
|
|
}
|
|
++DefIdx;
|
|
return; // Found a normal regdef.
|
|
}
|
|
Node = Node->getGluedNode();
|
|
if (Node == NULL) {
|
|
return; // No values left to visit.
|
|
}
|
|
InitNodeNumDefs();
|
|
}
|
|
}
|
|
|
|
void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
|
|
assert(SU->NumRegDefsLeft == 0 && "expect a new node");
|
|
for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
|
|
assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
|
|
++SU->NumRegDefsLeft;
|
|
}
|
|
}
|
|
|
|
void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
|
|
// Check to see if the scheduler cares about latencies.
|
|
if (ForceUnitLatencies()) {
|
|
SU->Latency = 1;
|
|
return;
|
|
}
|
|
|
|
if (!InstrItins || InstrItins->isEmpty()) {
|
|
SDNode *N = SU->getNode();
|
|
if (N && N->isMachineOpcode() &&
|
|
TII->isHighLatencyDef(N->getMachineOpcode()))
|
|
SU->Latency = HighLatencyCycles;
|
|
else
|
|
SU->Latency = 1;
|
|
return;
|
|
}
|
|
|
|
// Compute the latency for the node. We use the sum of the latencies for
|
|
// all nodes glued together into this SUnit.
|
|
SU->Latency = 0;
|
|
for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
|
|
if (N->isMachineOpcode())
|
|
SU->Latency += TII->getInstrLatency(InstrItins, N);
|
|
}
|
|
|
|
void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
|
|
unsigned OpIdx, SDep& dep) const{
|
|
// Check to see if the scheduler cares about latencies.
|
|
if (ForceUnitLatencies())
|
|
return;
|
|
|
|
if (dep.getKind() != SDep::Data)
|
|
return;
|
|
|
|
unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
|
|
if (Use->isMachineOpcode())
|
|
// Adjust the use operand index by num of defs.
|
|
OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
|
|
int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
|
|
if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
|
|
!BB->succ_empty()) {
|
|
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg))
|
|
// This copy is a liveout value. It is likely coalesced, so reduce the
|
|
// latency so not to penalize the def.
|
|
// FIXME: need target specific adjustment here?
|
|
Latency = (Latency > 1) ? Latency - 1 : 1;
|
|
}
|
|
if (Latency >= 0)
|
|
dep.setLatency(Latency);
|
|
}
|
|
|
|
void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
|
|
if (!SU->getNode()) {
|
|
dbgs() << "PHYS REG COPY\n";
|
|
return;
|
|
}
|
|
|
|
SU->getNode()->dump(DAG);
|
|
dbgs() << "\n";
|
|
SmallVector<SDNode *, 4> GluedNodes;
|
|
for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
|
|
GluedNodes.push_back(N);
|
|
while (!GluedNodes.empty()) {
|
|
dbgs() << " ";
|
|
GluedNodes.back()->dump(DAG);
|
|
dbgs() << "\n";
|
|
GluedNodes.pop_back();
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
struct OrderSorter {
|
|
bool operator()(const std::pair<unsigned, MachineInstr*> &A,
|
|
const std::pair<unsigned, MachineInstr*> &B) {
|
|
return A.first < B.first;
|
|
}
|
|
};
|
|
}
|
|
|
|
/// ProcessSDDbgValues - Process SDDbgValues assoicated with this node.
|
|
static void ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG,
|
|
InstrEmitter &Emitter,
|
|
SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap,
|
|
unsigned Order) {
|
|
if (!N->getHasDebugValue())
|
|
return;
|
|
|
|
// Opportunistically insert immediate dbg_value uses, i.e. those with source
|
|
// order number right after the N.
|
|
MachineBasicBlock *BB = Emitter.getBlock();
|
|
MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
|
|
SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N);
|
|
for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
|
|
if (DVs[i]->isInvalidated())
|
|
continue;
|
|
unsigned DVOrder = DVs[i]->getOrder();
|
|
if (!Order || DVOrder == ++Order) {
|
|
MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
|
|
if (DbgMI) {
|
|
Orders.push_back(std::make_pair(DVOrder, DbgMI));
|
|
BB->insert(InsertPos, DbgMI);
|
|
}
|
|
DVs[i]->setIsInvalidated();
|
|
}
|
|
}
|
|
}
|
|
|
|
// ProcessSourceNode - Process nodes with source order numbers. These are added
|
|
// to a vector which EmitSchedule uses to determine how to insert dbg_value
|
|
// instructions in the right order.
|
|
static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
|
|
InstrEmitter &Emitter,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap,
|
|
SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
|
|
SmallSet<unsigned, 8> &Seen) {
|
|
unsigned Order = DAG->GetOrdering(N);
|
|
if (!Order || !Seen.insert(Order)) {
|
|
// Process any valid SDDbgValues even if node does not have any order
|
|
// assigned.
|
|
ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
|
|
return;
|
|
}
|
|
|
|
MachineBasicBlock *BB = Emitter.getBlock();
|
|
if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {
|
|
// Did not insert any instruction.
|
|
Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
|
|
return;
|
|
}
|
|
|
|
Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
|
|
ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
|
|
}
|
|
|
|
|
|
/// EmitSchedule - Emit the machine code in scheduled order.
|
|
MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
|
|
InstrEmitter Emitter(BB, InsertPos);
|
|
DenseMap<SDValue, unsigned> VRBaseMap;
|
|
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
|
|
SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
|
|
SmallSet<unsigned, 8> Seen;
|
|
bool HasDbg = DAG->hasDebugValues();
|
|
|
|
// If this is the first BB, emit byval parameter dbg_value's.
|
|
if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
|
|
SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
|
|
SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
|
|
for (; PDI != PDE; ++PDI) {
|
|
MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
|
|
if (DbgMI)
|
|
BB->insert(InsertPos, DbgMI);
|
|
}
|
|
}
|
|
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
SUnit *SU = Sequence[i];
|
|
if (!SU) {
|
|
// Null SUnit* is a noop.
|
|
EmitNoop();
|
|
continue;
|
|
}
|
|
|
|
// For pre-regalloc scheduling, create instructions corresponding to the
|
|
// SDNode and any glued SDNodes and append them to the block.
|
|
if (!SU->getNode()) {
|
|
// Emit a copy.
|
|
EmitPhysRegCopy(SU, CopyVRBaseMap);
|
|
continue;
|
|
}
|
|
|
|
SmallVector<SDNode *, 4> GluedNodes;
|
|
for (SDNode *N = SU->getNode()->getGluedNode(); N;
|
|
N = N->getGluedNode())
|
|
GluedNodes.push_back(N);
|
|
while (!GluedNodes.empty()) {
|
|
SDNode *N = GluedNodes.back();
|
|
Emitter.EmitNode(GluedNodes.back(), SU->OrigNode != SU, SU->isCloned,
|
|
VRBaseMap);
|
|
// Remember the source order of the inserted instruction.
|
|
if (HasDbg)
|
|
ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
|
|
GluedNodes.pop_back();
|
|
}
|
|
Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
|
|
VRBaseMap);
|
|
// Remember the source order of the inserted instruction.
|
|
if (HasDbg)
|
|
ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
|
|
Seen);
|
|
}
|
|
|
|
// Insert all the dbg_values which have not already been inserted in source
|
|
// order sequence.
|
|
if (HasDbg) {
|
|
MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
|
|
|
|
// Sort the source order instructions and use the order to insert debug
|
|
// values.
|
|
std::sort(Orders.begin(), Orders.end(), OrderSorter());
|
|
|
|
SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
|
|
SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
|
|
// Now emit the rest according to source order.
|
|
unsigned LastOrder = 0;
|
|
for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
|
|
unsigned Order = Orders[i].first;
|
|
MachineInstr *MI = Orders[i].second;
|
|
// Insert all SDDbgValue's whose order(s) are before "Order".
|
|
if (!MI)
|
|
continue;
|
|
for (; DI != DE &&
|
|
(*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
|
|
if ((*DI)->isInvalidated())
|
|
continue;
|
|
MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
|
|
if (DbgMI) {
|
|
if (!LastOrder)
|
|
// Insert to start of the BB (after PHIs).
|
|
BB->insert(BBBegin, DbgMI);
|
|
else {
|
|
// Insert at the instruction, which may be in a different
|
|
// block, if the block was split by a custom inserter.
|
|
MachineBasicBlock::iterator Pos = MI;
|
|
MI->getParent()->insert(llvm::next(Pos), DbgMI);
|
|
}
|
|
}
|
|
}
|
|
LastOrder = Order;
|
|
}
|
|
// Add trailing DbgValue's before the terminator. FIXME: May want to add
|
|
// some of them before one or more conditional branches?
|
|
while (DI != DE) {
|
|
MachineBasicBlock *InsertBB = Emitter.getBlock();
|
|
MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
|
|
if (!(*DI)->isInvalidated()) {
|
|
MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap);
|
|
if (DbgMI)
|
|
InsertBB->insert(Pos, DbgMI);
|
|
}
|
|
++DI;
|
|
}
|
|
}
|
|
|
|
BB = Emitter.getBlock();
|
|
InsertPos = Emitter.getInsertPos();
|
|
return BB;
|
|
}
|