llvm-6502/test/CodeGen/X86/atom-bypass-slow-division-64.ll
Benjamin Kramer 4eed756153 Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.
The main advantages here are way better heuristics, taking into account not
just loop depth but also __builtin_expect and other static heuristics and will
eventually learn how to use profile info. Most of the work in this patch is
pushing the MachineBlockFrequencyInfo analysis into the right places.

This is good for a 5% speedup on zlib's deflate (x86_64), there were some very
unfortunate spilling decisions in its hottest loop in longest_match(). Other
benchmarks I tried were mostly neutral.

This changes register allocation in subtle ways, update the tests for it.
2012-02-20-MachineCPBug.ll was deleted as it's very fragile and the instruction
it looked for was gone already (but the FileCheck pattern picked up unrelated
stuff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-17 19:00:36 +00:00

50 lines
1.1 KiB
LLVM

; RUN: llc < %s -mcpu=atom -mtriple=i686-linux -march=x86-64 | FileCheck %s
; Additional tests for 64-bit divide bypass
define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
; CHECK: Test_get_quotient:
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
; CHECK-NEXT: je
; CHECK: idivq
; CHECK: ret
; CHECK: divw
; CHECK: ret
%result = sdiv i64 %a, %b
ret i64 %result
}
define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
; CHECK: Test_get_remainder:
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
; CHECK-NEXT: je
; CHECK: idivq
; CHECK: ret
; CHECK: divw
; CHECK: ret
%result = srem i64 %a, %b
ret i64 %result
}
define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
; CHECK: Test_get_quotient_and_remainder:
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
; CHECK-NEXT: je
; CHECK: idivq
; CHECK: divw
; CHECK: addq
; CHECK: ret
; CHECK-NOT: idivq
; CHECK-NOT: divw
%resultdiv = sdiv i64 %a, %b
%resultrem = srem i64 %a, %b
%result = add i64 %resultdiv, %resultrem
ret i64 %result
}