Vincent Lejeune 8e37705a73 R600: Avoid more than 4 literals in the same instruction group at scheduling ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187515 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-31 19:32:07 +00:00
..
AArch64	AArch64: add llc-based tests for previous commit.	2013-07-25 16:23:55 +00:00
ARM	This test may have been sensitive to the ARM ABI...	2013-07-30 20:34:59 +00:00
CPP
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Inputs	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Mips	[mips] Implement llvm.trap intrinsic.	2013-07-26 20:58:55 +00:00
MSP430	Use conventional syntax for branches.	2013-07-14 18:19:44 +00:00
NVPTX	Add a target legalize hook for SplitVectorOperand (again)	2013-07-26 13:28:29 +00:00
PowerPC	PPC32 va_list is an actual structure so va_copy needs to copy the whole	2013-07-25 21:36:47 +00:00
R600	R600: Avoid more than 4 literals in the same instruction group at scheduling	2013-07-31 19:32:07 +00:00
SI
SPARC	Allocate local registers in order for optimal coloring.	2013-07-25 18:35:14 +00:00
SystemZ	[SystemZ] Implement isLegalAddressingMode()	2013-07-31 12:58:26 +00:00
Thumb	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Thumb2	Refactor AnalyzeBranch on ARM. The previous version did not always analyze	2013-07-19 23:52:47 +00:00
X86	Added INSERT and EXTRACT intructions from AVX-512 ISA.	2013-07-31 11:35:14 +00:00
XCore	Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change.	2013-07-18 22:29:15 +00:00