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81a0382181
When a live interval is being spilled, rather than creating short, non-spillable intervals for every def / use, split the interval at BB boundaries. That is, for every BB where the live interval is defined or used, create a new interval that covers all the defs and uses in the BB. This is designed to eliminate one common problem: multiple reloads of the same value in a single basic block. Note, it does *not* decrease the number of spills since no copies are inserted so the split intervals are *connected* through spill and reloads (or rematerialization). The newly created intervals can be spilled again, in that case, since it does not span multiple basic blocks, it's spilled in the usual manner. However, it can reuse the same stack slot as the previously split interval. This is currently controlled by -split-intervals-at-bb. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44198 91177308-0d34-0410-b5e6-96231b3b80d8
696 lines
26 KiB
C++
696 lines
26 KiB
C++
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveVariable analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using are sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Config/alloca.h"
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#include <algorithm>
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using namespace llvm;
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char LiveVariables::ID = 0;
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static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
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void LiveVariables::VarInfo::dump() const {
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cerr << "Register Defined by: ";
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if (DefInst)
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cerr << *DefInst;
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else
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cerr << "<null>\n";
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cerr << " Alive in blocks: ";
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for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
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if (AliveBlocks[i]) cerr << i << ", ";
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cerr << " Used in blocks: ";
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for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
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if (UsedBlocks[i]) cerr << i << ", ";
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cerr << "\n Killed by:";
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if (Kills.empty())
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cerr << " No instructions.\n";
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else {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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cerr << "\n #" << i << ": " << *Kills[i];
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cerr << "\n";
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}
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}
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
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"getVarInfo: not a virtual register!");
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RegIdx -= MRegisterInfo::FirstVirtualRegister;
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if (RegIdx >= VirtRegInfo.size()) {
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if (RegIdx >= 2*VirtRegInfo.size())
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VirtRegInfo.resize(RegIdx*2);
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else
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VirtRegInfo.resize(2*VirtRegInfo.size());
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}
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VarInfo &VI = VirtRegInfo[RegIdx];
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VI.AliveBlocks.resize(MF->getNumBlockIDs());
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VI.UsedBlocks.resize(MF->getNumBlockIDs());
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return VI;
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}
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bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isKill()) {
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if ((MO.getReg() == Reg) ||
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(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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MRegisterInfo::isPhysicalRegister(Reg) &&
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RegInfo->isSubRegister(MO.getReg(), Reg)))
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return true;
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}
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}
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return false;
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}
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bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDead()) {
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if ((MO.getReg() == Reg) ||
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(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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MRegisterInfo::isPhysicalRegister(Reg) &&
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RegInfo->isSubRegister(MO.getReg(), Reg)))
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return true;
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}
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}
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return false;
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}
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bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
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return true;
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}
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return false;
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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MachineBasicBlock *MBB,
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std::vector<MachineBasicBlock*> &WorkList) {
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unsigned BBNum = MBB->getNumber();
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// Check to see if this basic block is one of the killing blocks. If so,
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// remove it...
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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if (VRInfo.Kills[i]->getParent() == MBB) {
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
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if (VRInfo.AliveBlocks[BBNum])
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks[BBNum] = true;
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for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
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E = MBB->pred_rend(); PI != E; ++PI)
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WorkList.push_back(*PI);
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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MachineBasicBlock *MBB) {
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std::vector<MachineBasicBlock*> WorkList;
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MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList);
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while (!WorkList.empty()) {
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MachineBasicBlock *Pred = WorkList.back();
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WorkList.pop_back();
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MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList);
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}
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}
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void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
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MachineInstr *MI) {
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assert(VRInfo.DefInst && "Register use before def!");
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unsigned BBNum = MBB->getNumber();
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VRInfo.UsedBlocks[BBNum] = true;
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VRInfo.NumUses++;
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// Check to see if this basic block is already a kill block...
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
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// Yes, this register is killed in this basic block already. Increase the
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// live range by updating the kill instruction.
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VRInfo.Kills.back() = MI;
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return;
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}
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
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#endif
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assert(MBB != VRInfo.DefInst->getParent() &&
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"Should have kill for defblock!");
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// Add a new kill entry for this basic block.
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// If this virtual register is already marked as alive in this basic block,
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// that means it is alive in at least one of the successor block, it's not
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// a kill.
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if (!VRInfo.AliveBlocks[BBNum])
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VRInfo.Kills.push_back(MI);
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// Update all dominating blocks to mark them known live.
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, *PI);
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}
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bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
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const MRegisterInfo *RegInfo,
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bool AddIfNotFound) {
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bool Found = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isUse()) {
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (Reg == IncomingReg) {
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MO.setIsKill();
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Found = true;
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break;
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} else if (MRegisterInfo::isPhysicalRegister(Reg) &&
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MRegisterInfo::isPhysicalRegister(IncomingReg) &&
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RegInfo->isSuperRegister(IncomingReg, Reg) &&
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MO.isKill())
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// A super-register kill already exists.
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Found = true;
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}
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}
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// If not found, this means an alias of one of the operand is killed. Add a
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// new implicit operand if required.
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if (!Found && AddIfNotFound) {
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MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
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return true;
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}
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return Found;
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}
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bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
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const MRegisterInfo *RegInfo,
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bool AddIfNotFound) {
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bool Found = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef()) {
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (Reg == IncomingReg) {
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MO.setIsDead();
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Found = true;
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break;
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} else if (MRegisterInfo::isPhysicalRegister(Reg) &&
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MRegisterInfo::isPhysicalRegister(IncomingReg) &&
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RegInfo->isSuperRegister(IncomingReg, Reg) &&
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MO.isDead())
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// There exists a super-register that's marked dead.
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return true;
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}
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}
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// If not found, this means an alias of one of the operand is dead. Add a
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// new implicit operand.
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if (!Found && AddIfNotFound) {
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MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
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true/*IsDead*/);
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return true;
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}
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return Found;
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}
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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// Turn previous partial def's into read/mod/write.
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for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
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MachineInstr *Def = PhysRegPartDef[Reg][i];
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// First one is just a def. This means the use is reading some undef bits.
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if (i != 0)
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Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
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Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
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}
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PhysRegPartDef[Reg].clear();
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// There was an earlier def of a super-register. Add implicit def to that MI.
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// A: EAX = ...
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// B: = AX
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// Add implicit def to A.
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if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
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!PhysRegUsed[Reg]) {
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MachineInstr *Def = PhysRegInfo[Reg];
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if (!Def->findRegisterDefOperand(Reg))
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Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
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}
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// There is a now a proper use, forget about the last partial use.
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PhysRegPartUse[Reg] = NULL;
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = true;
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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PhysRegInfo[SubReg] = MI;
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PhysRegUsed[SubReg] = true;
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}
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for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
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unsigned SuperReg = *SuperRegs; ++SuperRegs) {
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// Remember the partial use of this superreg if it was previously defined.
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bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
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if (!HasPrevDef) {
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for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
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unsigned SSReg = *SSRegs; ++SSRegs) {
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if (PhysRegInfo[SSReg] != NULL) {
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HasPrevDef = true;
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break;
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}
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}
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}
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if (HasPrevDef) {
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PhysRegInfo[SuperReg] = MI;
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PhysRegPartUse[SuperReg] = MI;
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}
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}
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}
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
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SmallSet<unsigned, 4> &SubKills) {
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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MachineInstr *LastRef = PhysRegInfo[SubReg];
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if (LastRef != RefMI ||
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!HandlePhysRegKill(SubReg, RefMI, SubKills))
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SubKills.insert(SubReg);
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}
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if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
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// No sub-registers, just check if reg is killed by RefMI.
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if (PhysRegInfo[Reg] == RefMI)
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return true;
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} else if (SubKills.empty())
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// None of the sub-registers are killed elsewhere...
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return true;
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return false;
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}
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void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
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SmallSet<unsigned, 4> &SubKills) {
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if (SubKills.count(Reg) == 0)
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addRegisterKilled(Reg, MI, RegInfo, true);
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else {
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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addRegisterKills(SubReg, MI, SubKills);
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}
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}
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
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SmallSet<unsigned, 4> SubKills;
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if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
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addRegisterKilled(Reg, RefMI, RegInfo, true);
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return true;
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} else {
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// Some sub-registers are killed by another MI.
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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addRegisterKills(SubReg, RefMI, SubKills);
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return false;
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}
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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// Does this kill a previous version of this register?
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if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
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if (PhysRegUsed[Reg]) {
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if (!HandlePhysRegKill(Reg, LastRef)) {
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if (PhysRegPartUse[Reg])
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addRegisterKilled(Reg, PhysRegPartUse[Reg], RegInfo, true);
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}
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} else if (PhysRegPartUse[Reg])
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// Add implicit use / kill to last partial use.
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addRegisterKilled(Reg, PhysRegPartUse[Reg], RegInfo, true);
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else if (LastRef != MI)
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// Defined, but not used. However, watch out for cases where a super-reg
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// is also defined on the same MI.
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addRegisterDead(Reg, LastRef, RegInfo);
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}
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
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if (PhysRegUsed[SubReg]) {
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if (!HandlePhysRegKill(SubReg, LastRef)) {
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if (PhysRegPartUse[SubReg])
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addRegisterKilled(SubReg, PhysRegPartUse[SubReg], RegInfo, true);
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}
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} else if (PhysRegPartUse[SubReg])
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// Add implicit use / kill to last use of a sub-register.
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addRegisterKilled(SubReg, PhysRegPartUse[SubReg], RegInfo, true);
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else if (LastRef != MI)
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// This must be a def of the subreg on the same MI.
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addRegisterDead(SubReg, LastRef, RegInfo);
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}
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}
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if (MI) {
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for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
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unsigned SuperReg = *SuperRegs; ++SuperRegs) {
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if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
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// The larger register is previously defined. Now a smaller part is
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// being re-defined. Treat it as read/mod/write.
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// EAX =
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// AX = EAX<imp-use,kill>, EAX<imp-def>
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MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
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MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
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PhysRegInfo[SuperReg] = MI;
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PhysRegUsed[SuperReg] = false;
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PhysRegPartUse[SuperReg] = NULL;
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} else {
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// Remember this partial def.
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PhysRegPartDef[SuperReg].push_back(MI);
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}
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}
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = false;
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PhysRegPartDef[Reg].clear();
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PhysRegPartUse[Reg] = NULL;
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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PhysRegInfo[SubReg] = MI;
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PhysRegUsed[SubReg] = false;
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PhysRegPartDef[SubReg].clear();
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PhysRegPartUse[SubReg] = NULL;
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}
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}
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}
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bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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RegInfo = MF->getTarget().getRegisterInfo();
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assert(RegInfo && "Target doesn't have register information?");
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ReservedRegisters = RegInfo->getReservedRegs(mf);
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unsigned NumRegs = RegInfo->getNumRegs();
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PhysRegInfo = new MachineInstr*[NumRegs];
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PhysRegUsed = new bool[NumRegs];
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PhysRegPartUse = new MachineInstr*[NumRegs];
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PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
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PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
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std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
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std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
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/// Get some space for a respectable number of registers...
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VirtRegInfo.resize(64);
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analyzePHINodes(mf);
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// Calculate live variable information in depth first order on the CFG of the
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// function. This guarantees that we will see the definition of a virtual
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// register before its uses due to dominance properties of SSA (except for PHI
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|
// nodes, which are treated as a special case).
|
|
//
|
|
MachineBasicBlock *Entry = MF->begin();
|
|
SmallPtrSet<MachineBasicBlock*,16> Visited;
|
|
for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
|
|
DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
|
|
DFI != E; ++DFI) {
|
|
MachineBasicBlock *MBB = *DFI;
|
|
|
|
// Mark live-in registers as live-in.
|
|
for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
|
|
EE = MBB->livein_end(); II != EE; ++II) {
|
|
assert(MRegisterInfo::isPhysicalRegister(*II) &&
|
|
"Cannot have a live-in virtual register!");
|
|
HandlePhysRegDef(*II, 0);
|
|
}
|
|
|
|
// Loop over all of the instructions, processing them.
|
|
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
|
|
I != E; ++I) {
|
|
MachineInstr *MI = I;
|
|
|
|
// Process all of the operands of the instruction...
|
|
unsigned NumOperandsToProcess = MI->getNumOperands();
|
|
|
|
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
|
|
// of the uses. They will be handled in other basic blocks.
|
|
if (MI->getOpcode() == TargetInstrInfo::PHI)
|
|
NumOperandsToProcess = 1;
|
|
|
|
// Process all uses...
|
|
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
|
|
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
|
|
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
|
|
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
|
!ReservedRegisters[MO.getReg()]) {
|
|
HandlePhysRegUse(MO.getReg(), MI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Process all defs...
|
|
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
|
|
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
VarInfo &VRInfo = getVarInfo(MO.getReg());
|
|
|
|
assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
|
|
VRInfo.DefInst = MI;
|
|
// Defaults to dead
|
|
VRInfo.Kills.push_back(MI);
|
|
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
|
!ReservedRegisters[MO.getReg()]) {
|
|
HandlePhysRegDef(MO.getReg(), MI);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Handle any virtual assignments from PHI nodes which might be at the
|
|
// bottom of this basic block. We check all of our successor blocks to see
|
|
// if they have PHI nodes, and if so, we simulate an assignment at the end
|
|
// of the current block.
|
|
if (!PHIVarInfo[MBB->getNumber()].empty()) {
|
|
SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
|
|
|
|
for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
|
|
E = VarInfoVec.end(); I != E; ++I) {
|
|
VarInfo& VRInfo = getVarInfo(*I);
|
|
assert(VRInfo.DefInst && "Register use before def (or no def)!");
|
|
|
|
// Only mark it alive only in the block we are representing.
|
|
MarkVirtRegAliveInBlock(VRInfo, MBB);
|
|
}
|
|
}
|
|
|
|
// Finally, if the last instruction in the block is a return, make sure to mark
|
|
// it as using all of the live-out values in the function.
|
|
if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
|
|
MachineInstr *Ret = &MBB->back();
|
|
for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
|
|
E = MF->liveout_end(); I != E; ++I) {
|
|
assert(MRegisterInfo::isPhysicalRegister(*I) &&
|
|
"Cannot have a live-in virtual register!");
|
|
HandlePhysRegUse(*I, Ret);
|
|
// Add live-out registers as implicit uses.
|
|
if (Ret->findRegisterUseOperandIdx(*I) == -1)
|
|
Ret->addRegOperand(*I, false, true);
|
|
}
|
|
}
|
|
|
|
// Loop over PhysRegInfo, killing any registers that are available at the
|
|
// end of the basic block. This also resets the PhysRegInfo map.
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
if (PhysRegInfo[i])
|
|
HandlePhysRegDef(i, 0);
|
|
|
|
// Clear some states between BB's. These are purely local information.
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
PhysRegPartDef[i].clear();
|
|
std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
|
|
std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
|
|
std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
|
|
}
|
|
|
|
// Convert and transfer the dead / killed information we have gathered into
|
|
// VirtRegInfo onto MI's.
|
|
//
|
|
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
|
|
for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
|
|
if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
|
|
addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
|
|
VirtRegInfo[i].Kills[j], RegInfo);
|
|
else
|
|
addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister,
|
|
VirtRegInfo[i].Kills[j], RegInfo);
|
|
}
|
|
|
|
// Check to make sure there are no unreachable blocks in the MC CFG for the
|
|
// function. If so, it is due to a bug in the instruction selector or some
|
|
// other part of the code generator if this happens.
|
|
#ifndef NDEBUG
|
|
for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
|
|
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
|
|
#endif
|
|
|
|
delete[] PhysRegInfo;
|
|
delete[] PhysRegUsed;
|
|
delete[] PhysRegPartUse;
|
|
delete[] PhysRegPartDef;
|
|
delete[] PHIVarInfo;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// instructionChanged - When the address of an instruction changes, this
|
|
/// method should be called so that live variables can update its internal
|
|
/// data structures. This removes the records for OldMI, transfering them to
|
|
/// the records for NewMI.
|
|
void LiveVariables::instructionChanged(MachineInstr *OldMI,
|
|
MachineInstr *NewMI) {
|
|
// If the instruction defines any virtual registers, update the VarInfo,
|
|
// kill and dead information for the instruction.
|
|
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = OldMI->getOperand(i);
|
|
if (MO.isRegister() && MO.getReg() &&
|
|
MRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
unsigned Reg = MO.getReg();
|
|
VarInfo &VI = getVarInfo(Reg);
|
|
if (MO.isDef()) {
|
|
if (MO.isDead()) {
|
|
MO.unsetIsDead();
|
|
addVirtualRegisterDead(Reg, NewMI);
|
|
}
|
|
// Update the defining instruction.
|
|
if (VI.DefInst == OldMI)
|
|
VI.DefInst = NewMI;
|
|
}
|
|
if (MO.isKill()) {
|
|
MO.unsetIsKill();
|
|
addVirtualRegisterKilled(Reg, NewMI);
|
|
}
|
|
// If this is a kill of the value, update the VI kills list.
|
|
if (VI.removeKill(OldMI))
|
|
VI.Kills.push_back(NewMI); // Yes, there was a kill of it
|
|
}
|
|
}
|
|
}
|
|
|
|
/// transferKillDeadInfo - Similar to instructionChanged except it does not
|
|
/// update live variables internal data structures.
|
|
void LiveVariables::transferKillDeadInfo(MachineInstr *OldMI,
|
|
MachineInstr *NewMI,
|
|
const MRegisterInfo *RegInfo) {
|
|
// If the instruction defines any virtual registers, update the VarInfo,
|
|
// kill and dead information for the instruction.
|
|
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = OldMI->getOperand(i);
|
|
if (MO.isRegister() && MO.getReg() &&
|
|
MRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
unsigned Reg = MO.getReg();
|
|
if (MO.isDef()) {
|
|
if (MO.isDead()) {
|
|
MO.unsetIsDead();
|
|
addRegisterDead(Reg, NewMI, RegInfo);
|
|
}
|
|
}
|
|
if (MO.isKill()) {
|
|
MO.unsetIsKill();
|
|
addRegisterKilled(Reg, NewMI, RegInfo);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/// removeVirtualRegistersKilled - Remove all killed info for the specified
|
|
/// instruction.
|
|
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isKill()) {
|
|
MO.unsetIsKill();
|
|
unsigned Reg = MO.getReg();
|
|
if (MRegisterInfo::isVirtualRegister(Reg)) {
|
|
bool removed = getVarInfo(Reg).removeKill(MI);
|
|
assert(removed && "kill not in register's VarInfo?");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// removeVirtualRegistersDead - Remove all of the dead registers for the
|
|
/// specified instruction from the live variable information.
|
|
void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isDead()) {
|
|
MO.unsetIsDead();
|
|
unsigned Reg = MO.getReg();
|
|
if (MRegisterInfo::isVirtualRegister(Reg)) {
|
|
bool removed = getVarInfo(Reg).removeKill(MI);
|
|
assert(removed && "kill not in register's VarInfo?");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in here. In
|
|
/// particular, we want to map the variable information of a virtual
|
|
/// register which is used in a PHI node. We map that to the BB the vreg is
|
|
/// coming from.
|
|
///
|
|
void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
|
|
for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
|
|
I != E; ++I)
|
|
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
|
|
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
|
|
PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
|
|
push_back(BBI->getOperand(i).getReg());
|
|
}
|