Matheus Almeida 8e7aa4be58 [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions. ...

This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-26 16:09:43 +00:00

..

AArch64

[AArch64]Fix improper diagnostics about offset range of load/store instructions.

2014-03-04 02:05:13 +00:00

ARM

Teach llvm-readobj to print human friendly description of reserved sections.

2014-03-24 05:00:34 +00:00

AsmParser

Move tests that require ARM to an ARM test directory.

2014-03-18 22:43:59 +00:00

COFF

Object/COFF: change data type of SymbolNumber from int16 to uint16.

2014-03-15 00:04:08 +00:00

Disassembler

[SystemZ] Add support for z196 float<->unsigned conversions

2014-03-21 10:56:30 +00:00

ELF

Correctly detect if a symbol uses a reserved section index or not.

2014-03-26 00:16:43 +00:00

MachO

Fix crashes when assembler directives are used that are not

2014-03-25 00:05:50 +00:00

Markup

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Mips

[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.

2014-03-26 16:09:43 +00:00

PowerPC

[PowerPC] Generate little-endian object files

2014-03-24 18:16:09 +00:00

Sparc

[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.

2014-03-02 23:39:07 +00:00

SystemZ

[SystemZ] Add support for z196 float<->unsigned conversions

2014-03-21 10:56:30 +00:00

X86

Convert a CodeGen test into a MC test.

2014-03-21 00:55:42 +00:00