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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123768 91177308-0d34-0410-b5e6-96231b3b80d8
315 lines
12 KiB
C++
315 lines
12 KiB
C++
//=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsFrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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//
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// Stack Frame Processing methods
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// +----------------------------+
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//
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// The stack is allocated decrementing the stack pointer on
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// the first instruction of a function prologue. Once decremented,
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// all stack references are done thought a positive offset
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// from the stack/frame pointer, so the stack is considering
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// to grow up! Otherwise terrible hacks would have to be made
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// to get this stack ABI compliant :)
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//
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// The stack frame required by the ABI (after call):
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// Offset
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//
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// 0 ----------
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// 4 Args to pass
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// . saved $GP (used in PIC)
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// . Alloca allocations
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// . Local Area
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// . CPU "Callee Saved" Registers
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// . saved FP
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// . saved RA
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// . FPU "Callee Saved" Registers
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// StackSize -----------
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//
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// Offset - offset from sp after stack allocation on function prologue
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//
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// The sp is the stack pointer subtracted/added from the stack size
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// at the Prologue/Epilogue
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//
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// References to the previous stack (to obtain arguments) are done
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// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
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//
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// Examples:
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// - reference to the actual stack frame
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// for any local area var there is smt like : FI >= 0, StackOffset: 4
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// sw REGX, 4(SP)
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//
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// - reference to previous stack frame
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// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
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// The emitted instruction will be something like:
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// lw REGX, 16+StackSize(SP)
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//
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// Since the total stack size is unknown on LowerFormalArguments, all
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// stack references (ObjectOffset) created to reference the function
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// arguments, are negative numbers. This way, on eliminateFrameIndex it's
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// possible to detect those references and the offsets are adjusted to
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// their real location.
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//
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
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}
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void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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unsigned StackAlign = getStackAlignment();
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unsigned RegSize = STI.isGP32bit() ? 4 : 8;
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bool HasGP = MipsFI->needGPSaveRestore();
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// Min and Max CSI FrameIndex.
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int MinCSFI = -1, MaxCSFI = -1;
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// See the description at MipsMachineFunction.h
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int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
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// Replace the dummy '0' SPOffset by the negative offsets, as explained on
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// LowerFormalArguments. Leaving '0' for while is necessary to avoid the
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// approach done by calculateFrameObjectOffsets to the stack frame.
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MipsFI->adjustLoadArgsFI(MFI);
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MipsFI->adjustStoreVarArgsFI(MFI);
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// It happens that the default stack frame allocation order does not directly
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// map to the convention used for mips. So we must fix it. We move the callee
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// save register slots after the local variables area, as described in the
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// stack frame above.
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unsigned CalleeSavedAreaSize = 0;
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if (!CSI.empty()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
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}
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for (unsigned i = 0, e = CSI.size(); i != e; ++i)
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CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
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unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize)
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: (STI.isABI_O32() ? 16 : 0);
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// Adjust local variables. They should come on the stack right
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// after the arguments.
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int LastOffsetFI = -1;
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for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
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if (i >= MinCSFI && i <= MaxCSFI)
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continue;
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if (MFI->isDeadObjectIndex(i))
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continue;
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unsigned Offset =
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StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize;
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if (LastOffsetFI == -1)
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LastOffsetFI = i;
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if (Offset > MFI->getObjectOffset(LastOffsetFI))
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LastOffsetFI = i;
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MFI->setObjectOffset(i, Offset);
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}
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// Adjust CPU Callee Saved Registers Area. Registers RA and FP must
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// be saved in this CPU Area. This whole area must be aligned to the
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// default Stack Alignment requirements.
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if (LastOffsetFI >= 0)
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StackOffset = MFI->getObjectOffset(LastOffsetFI)+
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MFI->getObjectSize(LastOffsetFI);
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StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
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for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (!Mips::CPURegsRegisterClass->contains(Reg))
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break;
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MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
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TopCPUSavedRegOff = StackOffset;
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StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
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}
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// Stack locations for FP and RA. If only one of them is used,
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// the space must be allocated for both, otherwise no space at all.
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if (hasFP(MF) || MFI->adjustsStack()) {
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// FP stack location
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MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
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StackOffset);
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MipsFI->setFPStackOffset(StackOffset);
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TopCPUSavedRegOff = StackOffset;
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StackOffset += RegSize;
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// SP stack location
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MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
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StackOffset);
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MipsFI->setRAStackOffset(StackOffset);
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StackOffset += RegSize;
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if (MFI->adjustsStack())
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TopCPUSavedRegOff += RegSize;
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}
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StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
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// Adjust FPU Callee Saved Registers Area. This Area must be
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// aligned to the default Stack Alignment requirements.
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Mips::CPURegsRegisterClass->contains(Reg))
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continue;
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MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
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TopFPUSavedRegOff = StackOffset;
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StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
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}
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StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
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// Update frame info
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MFI->setStackSize(StackOffset);
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// Recalculate the final tops offset. The final values must be '0'
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// if there isn't a callee saved register for CPU or FPU, otherwise
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// a negative offset is needed.
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if (TopCPUSavedRegOff >= 0)
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MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
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if (TopFPUSavedRegOff >= 0)
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MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
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}
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void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
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// Get the right frame order for Mips.
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adjustMipsStackFrame(MF);
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// Get the number of bytes to allocate from the FrameInfo.
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unsigned StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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int FPOffset = MipsFI->getFPStackOffset();
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int RAOffset = MipsFI->getRAStackOffset();
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
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// TODO: check need from GP here.
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if (isPIC && STI.isABI_O32())
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BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
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.addReg(RegInfo->getPICCallReg());
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
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// Adjust stack : addi sp, sp, (-imm)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(-StackSize);
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// Save the return address only if the function isnt a leaf one.
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// sw $ra, stack_loc($sp)
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if (MFI->adjustsStack()) {
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BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
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.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
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}
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// if framepointer enabled, save it and set it
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// to point to the stack pointer
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if (hasFP(MF)) {
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// sw $fp,stack_loc($sp)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
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.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
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// move $fp, $sp
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
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.addReg(Mips::SP).addReg(Mips::ZERO);
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}
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// Restore GP from the saved stack location
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if (MipsFI->needGPSaveRestore())
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BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
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.addImm(MipsFI->getGPStackOffset());
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}
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void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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// Get the number of bytes from FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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// Get the FI's where RA and FP are saved.
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int FPOffset = MipsFI->getFPStackOffset();
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int RAOffset = MipsFI->getRAStackOffset();
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// if framepointer enabled, restore it and restore the
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// stack pointer
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if (hasFP(MF)) {
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// move $sp, $fp
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
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.addReg(Mips::FP).addReg(Mips::ZERO);
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// lw $fp,stack_loc($sp)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP)
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.addImm(FPOffset).addReg(Mips::SP);
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}
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// Restore the return address only if the function isnt a leaf one.
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// lw $ra, stack_loc($sp)
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if (MFI->adjustsStack()) {
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BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA)
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.addImm(RAOffset).addReg(Mips::SP);
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}
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// adjust stack : insert addi sp, sp, (imm)
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if (NumBytes) {
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(NumBytes);
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}
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}
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void MipsFrameLowering::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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RegInfo->processFunctionBeforeFrameFinalized(MF);
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}
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