Chandler Carruth 8e93ce1780 [x86] Add the dispatch skeleton to the new vector shuffle lowering for ... AVX-512. There is no interesting logic yet. Everything ends up eventually delegating to the generic code to split the vector and shuffle the halves. Interestingly, that logic does a significantly better job of lowering all of these types than the generic vector expansion code does. Mostly, it lets most of the cases fall back to nice AVX2 code rather than all the way back to SSE code paths. Step 2 of basic AVX-512 support in the new vector shuffle lowering. Next up will be to incrementally add direct support for the basic instruction set to each type (adding tests first). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218585 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-29 00:37:27 +00:00
..
AArch64	[AArch64] Redundant store instructions should be removed as dead code	2014-09-27 17:02:54 +00:00
ARM	Fix swift-atomics testcase	2014-09-23 23:18:01 +00:00
CPP
Generic	Fix crash with an insertvalue that produces an empty object.	2014-09-20 00:10:47 +00:00
Hexagon	Add missing attributes !cmp.[eq,gt,gtu] instructions.	2014-09-25 13:09:54 +00:00
Inputs
Mips	Add the first backend support for on demand subtarget creation	2014-09-26 01:44:08 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	Refactor reciprocal and reciprocal square root estimate into target-independent functions (part 2).	2014-09-26 23:01:47 +00:00
R600	R600/SI: Add strict check lines to div_scale tests.	2014-09-26 17:55:11 +00:00
SPARC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
SystemZ
Thumb	[Thumb] Make load/store optimizer less conservative.	2014-09-24 16:35:50 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[x86] Add the dispatch skeleton to the new vector shuffle lowering for	2014-09-29 00:37:27 +00:00
XCore