llvm-6502/test/CodeGen
Hal Finkel 8e9ba0e588 [PowerPC] Reuse a load operand in int->fp conversions
int->fp conversions on PPC must be done through memory loads and stores. On a
modern core, this process begins by storing the int value to memory, then
loading it using a (sometimes special) FP load instruction. Unfortunately, we
would do this even when the value to be converted was itself a load, and we can
just use that same memory location instead of copying it to another first.
There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs,
because the fp_to_int operand has not been lowered when the int_to_fp is being
lowered. We handle this specially by invoking fp_to_int's lowering logic
(partially) and getting the necessary memory location (some trivial refactoring
was done to make this possible).

This is all somewhat ugly, and it would be nice if some later CodeGen stage
could just clean this stuff up, but because doing so would involve modifying
target-specific nodes (or instructions), it is not immediately clear how that
would work.

Also, remove a related entry from the README.txt for which we now generate
reasonable code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225301 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 22:31:02 +00:00
..
AArch64 [AArch64] Improve codegen of store lane instructions by avoiding GPR usage. 2015-01-05 17:10:26 +00:00
ARM Emit the build attribute Tag_conformance. 2015-01-05 13:12:17 +00:00
CPP
Generic
Hexagon [Hexagon] Adding dealloc_return encoding and absolute address stores. 2015-01-06 16:15:15 +00:00
Inputs
Mips
MSP430
NVPTX
PowerPC [PowerPC] Reuse a load operand in int->fp conversions 2015-01-06 22:31:02 +00:00
R600 R600/SI: Insert s_waitcnt before s_barrier instructions. 2015-01-06 19:52:07 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [CodeGenPrepare] Improved logic to speculate calls to cttz/ctlz. 2015-01-06 17:41:18 +00:00
XCore