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c4af4638df
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
986 B
LLVM
40 lines
986 B
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK: t1
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; CHECK: mvn r0, #-2147483648
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; CHECK: add r0, r1
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; CHECK: cmp r2, #10
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; CHECK: it gt
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; CHECK: movgt r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK: t2
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; CHECK: add.w r0, r1, #-2147483648
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; CHECK: cmp r2, #10
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; CHECK: it gt
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; CHECK: movgt r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483648
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; CHECK: t3
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; CHECK: sub.w r0, r1, #10
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; CHECK: cmp r2, #10
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; CHECK: it gt
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; CHECK: movgt r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 10
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%tmp3 = sub i32 %b, %tmp2
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ret i32 %tmp3
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}
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