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fcd3c4065d
than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227102 91177308-0d34-0410-b5e6-96231b3b80d8
222 lines
6.8 KiB
LLVM
222 lines
6.8 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-NOFPXX
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; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-FPXX
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NOFPXX
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FPXX
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; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-NOFPXX
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; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX
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; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NOFPXX
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; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-NOFPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-NOFPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX
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declare double @dbl();
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; 4-FPXX: LLVM ERROR: FPXX is not permitted for the N32/N64 ABI's.
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; 64-FPXX: LLVM ERROR: FPXX is not permitted for the N32/N64 ABI's.
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define double @test1(double %d, ...) {
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ret double %d
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; ALL-LABEL: test1:
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; 32-NOFPXX: mtc1 $4, $f0
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; 32-NOFPXX: mtc1 $5, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $4, 0($sp)
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; 32-FPXX: sw $5, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $4, $f0
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; 32R2-NOFPXX: mthc1 $5, $f0
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; 32R2-FPXX: mtc1 $4, $f0
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; 32R2-FPXX: mthc1 $5, $f0
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; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
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; 4-NOFPXX: mov.d $f0, $f12
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; 64-NOFPXX: mov.d $f0, $f12
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}
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define double @test2(i32 %i, double %d) {
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ret double %d
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; ALL-LABEL: test2:
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; 32-NOFPXX: mtc1 $6, $f0
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; 32-NOFPXX: mtc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $6, $f0
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; 32R2-NOFPXX: mthc1 $7, $f0
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; 32R2-FPXX: mtc1 $6, $f0
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; 32R2-FPXX: mthc1 $7, $f0
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; 4-NOFPXX: mov.d $f0, $f13
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; 64-NOFPXX: mov.d $f0, $f13
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}
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define double @test3(float %f1, float %f2, double %d) {
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ret double %d
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; ALL-LABEL: test3:
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; 32-NOFPXX: mtc1 $6, $f0
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; 32-NOFPXX: mtc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $6, $f0
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; 32R2-NOFPXX: mthc1 $7, $f0
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; 32R2-FPXX: mtc1 $6, $f0
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; 32R2-FPXX: mthc1 $7, $f0
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; 4-NOFPXX: mov.d $f0, $f14
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; 64-NOFPXX: mov.d $f0, $f14
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}
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define double @test4(float %f, double %d, ...) {
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ret double %d
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; ALL-LABEL: test4:
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; 32-NOFPXX: mtc1 $6, $f0
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; 32-NOFPXX: mtc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $6, $f0
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; 32R2-NOFPXX: mthc1 $7, $f0
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; 32R2-FPXX: mtc1 $6, $f0
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; 32R2-FPXX: mthc1 $7, $f0
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; 4-NOFPXX: mov.d $f0, $f13
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; 64-NOFPXX: mov.d $f0, $f13
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}
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define double @test5() {
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ret double 0.000000e+00
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; ALL-LABEL: test5:
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; 32-NOFPXX: mtc1 $zero, $f0
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; 32-NOFPXX: mtc1 $zero, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $zero, 0($sp)
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; 32-FPXX: sw $zero, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $zero, $f0
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; 32R2-NOFPXX: mthc1 $zero, $f0
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; 32R2-FPXX: mtc1 $zero, $f0
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; 32R2-FPXX: mthc1 $zero, $f0
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; 4-NOFPXX: dmtc1 $zero, $f0
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; 64-NOFPXX: dmtc1 $zero, $f0
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}
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define double @test6(double %a, double %b, ...) {
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%1 = fsub double %a, %b
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ret double %1
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; ALL-LABEL: test6:
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; 32-NOFPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
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; 32-NOFPXX-DAG: mtc1 $5, ${{f[0-9]*[13579]}}
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; 32-NOFPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
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; 32-NOFPXX-DAG: mtc1 $7, ${{f[0-9]*[13579]}}
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; 32-NOFPXX: sub.d $f0, $[[T0]], $[[T1]]
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $[[T1:f[0-9]+]], 0($sp)
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; 32-FPXX: sw $4, 0($sp)
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; 32-FPXX: sw $5, 4($sp)
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; 32-FPXX: ldc1 $[[T0:f[0-9]+]], 0($sp)
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; 32-FPXX: sub.d $f0, $[[T0]], $[[T1]]
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; 32R2-NOFPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
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; 32R2-NOFPXX-DAG: mthc1 $5, $[[T0]]
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; 32R2-NOFPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
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; 32R2-NOFPXX-DAG: mthc1 $7, $[[T1]]
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; 32R2-NOFPXX: sub.d $f0, $[[T0]], $[[T1]]
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; 32R2-FPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
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; 32R2-FPXX-DAG: mthc1 $5, $[[T0]]
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; 32R2-FPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
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; 32R2-FPXX-DAG: mthc1 $7, $[[T1]]
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; 32R2-FPXX: sub.d $f0, $[[T0]], $[[T1]]
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; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
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; 4-NOFPXX: sub.d $f0, $f12, $f13
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; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
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; 64-NOFPXX: sub.d $f0, $f12, $f13
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}
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define double @move_from1(double %d) {
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%1 = call double @dbl()
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%2 = call double @test2(i32 0, double %1)
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ret double %2
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; ALL-LABEL: move_from1:
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; 32-NOFPXX-DAG: mfc1 $6, $f0
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; 32-NOFPXX-DAG: mfc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -32
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; 32-FPXX: sdc1 $f0, 16($sp)
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; 32-FPXX: lw $6, 16($sp)
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; FIXME: This store is redundant
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; 32-FPXX: sdc1 $f0, 16($sp)
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; 32-FPXX: lw $7, 20($sp)
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; 32R2-NOFPXX-DAG: mfc1 $6, $f0
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; 32R2-NOFPXX-DAG: mfhc1 $7, $f0
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; 32R2-FPXX-DAG: mfc1 $6, $f0
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; 32R2-FPXX-DAG: mfhc1 $7, $f0
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; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
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; We can't use inline assembly to force a copy either because trying to force
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; a copy to a GPR this way fails with ; "couldn't allocate input reg for
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; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
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; in a simple test.
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; 4-NOFPXX: mov.d $f13, $f0
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; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
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; We can't use inline assembly to force a copy either because trying to force
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; a copy to a GPR this way fails with ; "couldn't allocate input reg for
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; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
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; in a simple test.
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; 64-NOFPXX: mov.d $f13, $f0
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}
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