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7c9a7728d9
by its first field, but TableGen doesn't actually enforce creating it that way. TableGen sorts the records that will be used to create it by the names of the records, not the Name field of those records. This patch corrects the sort to use the "Name" field of the record as the sort key. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56106 91177308-0d34-0410-b5e6-96231b3b80d8
513 lines
15 KiB
C++
513 lines
15 KiB
C++
//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits subtarget enumerations.
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//
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//===----------------------------------------------------------------------===//
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#include "SubtargetEmitter.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Debug.h"
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#include <algorithm>
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using namespace llvm;
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//
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// Enumeration - Emit the specified class as an enumeration.
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//
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void SubtargetEmitter::Enumeration(std::ostream &OS,
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const char *ClassName,
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bool isBits) {
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// Get all records of class and sort
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std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
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std::sort(DefList.begin(), DefList.end(), LessRecord());
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// Open enumeration
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OS << "enum {\n";
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// For each record
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for (unsigned i = 0, N = DefList.size(); i < N;) {
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// Next record
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Record *Def = DefList[i];
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// Get and emit name
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OS << " " << Def->getName();
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// If bit flags then emit expression (1 << i)
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if (isBits) OS << " = " << " 1 << " << i;
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// Depending on 'if more in the list' emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// Close enumeration
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OS << "};\n";
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}
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//
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// FeatureKeyValues - Emit data of all the subtarget features. Used by the
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// command line.
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//
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void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) {
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// Gather and sort all the features
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std::vector<Record*> FeatureList =
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Records.getAllDerivedDefinitions("SubtargetFeature");
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std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
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// Begin feature table
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OS << "// Sorted (by key) array of values for CPU features.\n"
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<< "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n";
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// For each feature
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for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
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// Next feature
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Record *Feature = FeatureList[i];
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const std::string &Name = Feature->getName();
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const std::string &CommandLineName = Feature->getValueAsString("Name");
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const std::string &Desc = Feature->getValueAsString("Desc");
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if (CommandLineName.empty()) continue;
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// Emit as { "feature", "decription", feactureEnum, i1 | i2 | ... | in }
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OS << " { "
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<< "\"" << CommandLineName << "\", "
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<< "\"" << Desc << "\", "
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<< Name << ", ";
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const std::vector<Record*> &ImpliesList =
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Feature->getValueAsListOfDefs("Implies");
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if (ImpliesList.empty()) {
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OS << "0";
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} else {
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for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
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OS << ImpliesList[j]->getName();
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if (++j < M) OS << " | ";
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}
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}
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OS << " }";
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// Depending on 'if more in the list' emit comma
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if ((i + 1) < N) OS << ",";
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OS << "\n";
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}
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// End feature table
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OS << "};\n";
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// Emit size of table
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OS<<"\nenum {\n";
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OS<<" FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)\n";
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OS<<"};\n";
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}
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//
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// CPUKeyValues - Emit data of all the subtarget processors. Used by command
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// line.
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//
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void SubtargetEmitter::CPUKeyValues(std::ostream &OS) {
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// Gather and sort processor information
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std::vector<Record*> ProcessorList =
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Records.getAllDerivedDefinitions("Processor");
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std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
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// Begin processor table
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OS << "// Sorted (by key) array of values for CPU subtype.\n"
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<< "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
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// For each processor
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for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
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// Next processor
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Record *Processor = ProcessorList[i];
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const std::string &Name = Processor->getValueAsString("Name");
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const std::vector<Record*> &FeatureList =
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Processor->getValueAsListOfDefs("Features");
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// Emit as { "cpu", "description", f1 | f2 | ... fn },
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OS << " { "
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<< "\"" << Name << "\", "
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<< "\"Select the " << Name << " processor\", ";
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if (FeatureList.empty()) {
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OS << "0";
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} else {
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for (unsigned j = 0, M = FeatureList.size(); j < M;) {
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OS << FeatureList[j]->getName();
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if (++j < M) OS << " | ";
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}
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}
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// The "0" is for the "implies" section of this data structure.
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OS << ", 0 }";
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// Depending on 'if more in the list' emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// End processor table
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OS << "};\n";
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// Emit size of table
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OS<<"\nenum {\n";
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OS<<" SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV)\n";
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OS<<"};\n";
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}
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//
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// CollectAllItinClasses - Gathers and enumerates all the itinerary classes.
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// Returns itinerary class count.
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//
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unsigned SubtargetEmitter::CollectAllItinClasses(std::ostream &OS,
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std::map<std::string, unsigned> &ItinClassesMap) {
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// Gather and sort all itinerary classes
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std::vector<Record*> ItinClassList =
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Records.getAllDerivedDefinitions("InstrItinClass");
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std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
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// For each itinerary class
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unsigned N = ItinClassList.size();
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for (unsigned i = 0; i < N; i++) {
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// Next itinerary class
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const Record *ItinClass = ItinClassList[i];
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// Get name of itinerary class
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// Assign itinerary class a unique number
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ItinClassesMap[ItinClass->getName()] = i;
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}
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// Emit size of table
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OS<<"\nenum {\n";
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OS<<" ItinClassesSize = " << N << "\n";
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OS<<"};\n";
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// Return itinerary class count
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return N;
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}
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//
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// FormItineraryString - Compose a string containing the data initialization
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// for the specified itinerary. N is the number of stages.
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//
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void SubtargetEmitter::FormItineraryString(Record *ItinData,
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std::string &ItinString,
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unsigned &NStages) {
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// Get states list
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const std::vector<Record*> &StageList =
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ItinData->getValueAsListOfDefs("Stages");
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// For each stage
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unsigned N = NStages = StageList.size();
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for (unsigned i = 0; i < N;) {
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// Next stage
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const Record *Stage = StageList[i];
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// Form string as ,{ cycles, u1 | u2 | ... | un }
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int Cycles = Stage->getValueAsInt("Cycles");
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ItinString += " { " + itostr(Cycles) + ", ";
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// Get unit list
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const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
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// For each unit
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for (unsigned j = 0, M = UnitList.size(); j < M;) {
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// Add name and bitwise or
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ItinString += UnitList[j]->getName();
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if (++j < M) ItinString += " | ";
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}
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// Close off stage
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ItinString += " }";
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if (++i < N) ItinString += ", ";
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}
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}
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//
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// EmitStageData - Generate unique itinerary stages. Record itineraries for
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// processors.
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//
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void SubtargetEmitter::EmitStageData(std::ostream &OS,
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unsigned NItinClasses,
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std::map<std::string, unsigned> &ItinClassesMap,
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std::vector<std::vector<InstrItinerary> > &ProcList) {
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// Gather processor iteraries
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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// If just no itinerary then don't bother
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if (ProcItinList.size() < 2) return;
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// Begin stages table
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OS << "static const llvm::InstrStage Stages[] = {\n"
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" { 0, 0 }, // No itinerary\n";
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unsigned StageCount = 1;
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unsigned ItinEnum = 1;
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std::map<std::string, unsigned> ItinMap;
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for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
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// Next record
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Record *Proc = ProcItinList[i];
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// Get processor itinerary name
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const std::string &Name = Proc->getName();
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// Skip default
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if (Name == "NoItineraries") continue;
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// Create and expand processor itinerary to cover all itinerary classes
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std::vector<InstrItinerary> ItinList;
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ItinList.resize(NItinClasses);
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// Get itinerary data list
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std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
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// For each itinerary data
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for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
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// Next itinerary data
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Record *ItinData = ItinDataList[j];
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// Get string and stage count
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std::string ItinString;
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unsigned NStages;
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FormItineraryString(ItinData, ItinString, NStages);
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// Check to see if it already exists
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unsigned Find = ItinMap[ItinString];
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// If new itinerary
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if (Find == 0) {
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// Emit as { cycles, u1 | u2 | ... | un }, // index
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OS << ItinString << ", // " << ItinEnum << "\n";
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// Record Itin class number.
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ItinMap[ItinString] = Find = StageCount;
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StageCount += NStages;
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ItinEnum++;
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}
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// Set up itinerary as location and location + stage count
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InstrItinerary Intinerary = { Find, Find + NStages };
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// Locate where to inject into processor itinerary table
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const std::string &Name = ItinData->getValueAsDef("TheClass")->getName();
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Find = ItinClassesMap[Name];
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// Inject - empty slots will be 0, 0
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ItinList[Find] = Intinerary;
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}
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// Add process itinerary to list
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ProcList.push_back(ItinList);
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}
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// Closing stage
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OS << " { 0, 0 } // End itinerary\n";
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// End stages table
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OS << "};\n";
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// Emit size of table
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OS<<"\nenum {\n";
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OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage)\n";
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OS<<"};\n";
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}
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//
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// EmitProcessorData - Generate data for processor itineraries.
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//
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void SubtargetEmitter::EmitProcessorData(std::ostream &OS,
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std::vector<std::vector<InstrItinerary> > &ProcList) {
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// Get an iterator for processor itinerary stages
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std::vector<std::vector<InstrItinerary> >::iterator
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ProcListIter = ProcList.begin();
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// For each processor itinerary
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std::vector<Record*> Itins =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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for (unsigned i = 0, N = Itins.size(); i < N; i++) {
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// Next record
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Record *Itin = Itins[i];
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// Get processor itinerary name
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const std::string &Name = Itin->getName();
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// Skip default
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if (Name == "NoItineraries") continue;
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// Begin processor itinerary table
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OS << "\n";
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OS << "static const llvm::InstrItinerary " << Name << "[] = {\n";
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// For each itinerary class
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std::vector<InstrItinerary> &ItinList = *ProcListIter++;
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for (unsigned j = 0, M = ItinList.size(); j < M;) {
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InstrItinerary &Intinerary = ItinList[j];
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// Emit in the form of { first, last } // index
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if (Intinerary.First == 0) {
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OS << " { 0, 0 }";
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} else {
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OS << " { " << Intinerary.First << ", " << Intinerary.Last << " }";
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}
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// If more in list add comma
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if (++j < M) OS << ",";
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OS << " // " << (j - 1) << "\n";
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}
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// End processor itinerary table
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OS << "};\n";
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}
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}
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//
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// EmitProcessorLookup - generate cpu name to itinerary lookup table.
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//
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void SubtargetEmitter::EmitProcessorLookup(std::ostream &OS) {
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// Gather and sort processor information
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std::vector<Record*> ProcessorList =
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Records.getAllDerivedDefinitions("Processor");
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std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
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// Begin processor table
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OS << "\n";
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OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
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<< "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n";
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// For each processor
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for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
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// Next processor
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Record *Processor = ProcessorList[i];
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const std::string &Name = Processor->getValueAsString("Name");
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const std::string &ProcItin =
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Processor->getValueAsDef("ProcItin")->getName();
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// Emit as { "cpu", procinit },
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OS << " { "
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<< "\"" << Name << "\", "
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<< "(void *)&" << ProcItin;
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OS << " }";
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// Depending on ''if more in the list'' emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// End processor table
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OS << "};\n";
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// Emit size of table
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OS<<"\nenum {\n";
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OS<<" ProcItinKVSize = sizeof(ProcItinKV)/"
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"sizeof(llvm::SubtargetInfoKV)\n";
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OS<<"};\n";
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}
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//
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// EmitData - Emits all stages and itineries, folding common patterns.
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//
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void SubtargetEmitter::EmitData(std::ostream &OS) {
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std::map<std::string, unsigned> ItinClassesMap;
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std::vector<std::vector<InstrItinerary> > ProcList;
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// Enumerate all the itinerary classes
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unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap);
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// Make sure the rest is worth the effort
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HasItineraries = NItinClasses != 1; // Ignore NoItinerary.
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if (HasItineraries) {
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// Emit the stage data
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EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
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// Emit the processor itinerary data
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EmitProcessorData(OS, ProcList);
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// Emit the processor lookup data
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EmitProcessorLookup(OS);
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}
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}
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//
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// ParseFeaturesFunction - Produces a subtarget specific function for parsing
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// the subtarget features string.
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//
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void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) {
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std::vector<Record*> Features =
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Records.getAllDerivedDefinitions("SubtargetFeature");
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std::sort(Features.begin(), Features.end(), LessRecord());
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OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
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<< "// subtarget options.\n"
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<< "void llvm::";
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OS << Target;
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OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
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<< " const std::string &CPU) {\n"
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<< " SubtargetFeatures Features(FS);\n"
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<< " Features.setCPUIfNone(CPU);\n"
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<< " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n"
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<< " FeatureKV, FeatureKVSize);\n";
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for (unsigned i = 0; i < Features.size(); i++) {
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// Next record
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Record *R = Features[i];
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const std::string &Instance = R->getName();
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const std::string &Value = R->getValueAsString("Value");
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const std::string &Attribute = R->getValueAsString("Attribute");
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if (Value=="true" || Value=="false")
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OS << " if ((Bits & " << Instance << ") != 0) "
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<< Attribute << " = " << Value << ";\n";
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else
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OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute <<
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" < " << Value << ") " << Attribute << " = " << Value << ";\n";
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}
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if (HasItineraries) {
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OS << "\n"
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<< " InstrItinerary *Itinerary = (InstrItinerary *)"
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<< "Features.getInfo(ProcItinKV, ProcItinKVSize);\n"
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<< " InstrItins = InstrItineraryData(Stages, Itinerary);\n";
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}
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OS << "}\n";
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}
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//
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// SubtargetEmitter::run - Main subtarget enumeration emitter.
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//
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void SubtargetEmitter::run(std::ostream &OS) {
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Target = CodeGenTarget().getName();
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EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
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OS << "#include \"llvm/Target/SubtargetFeature.h\"\n";
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OS << "#include \"llvm/Target/TargetInstrItineraries.h\"\n\n";
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Enumeration(OS, "FuncUnit", true);
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OS<<"\n";
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// Enumeration(OS, "InstrItinClass", false);
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// OS<<"\n";
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Enumeration(OS, "SubtargetFeature", true);
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OS<<"\n";
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FeatureKeyValues(OS);
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OS<<"\n";
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CPUKeyValues(OS);
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OS<<"\n";
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EmitData(OS);
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OS<<"\n";
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ParseFeaturesFunction(OS);
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}
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