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It is OK for an alias live range to overlap if there is a copy to or from the physical register. CoalescerPair can work out if the copy is coalescable independently of the alias. This means that we can join with the actual destination interval instead of using the getOrigDstReg() hack. It is no longer necessary to merge clobber ranges into subregisters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107695 91177308-0d34-0410-b5e6-96231b3b80d8
190 lines
7.7 KiB
C++
190 lines
7.7 KiB
C++
//===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a simple register copy coalescing phase.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
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#define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/ADT/BitVector.h"
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namespace llvm {
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class SimpleRegisterCoalescing;
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class LiveVariables;
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class TargetRegisterInfo;
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class TargetInstrInfo;
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class VirtRegMap;
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class MachineLoopInfo;
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/// CopyRec - Representation for copy instructions in coalescer queue.
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///
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struct CopyRec {
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MachineInstr *MI;
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unsigned LoopDepth;
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CopyRec(MachineInstr *mi, unsigned depth)
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: MI(mi), LoopDepth(depth) {}
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};
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class SimpleRegisterCoalescing : public MachineFunctionPass,
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public RegisterCoalescer {
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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LiveIntervals *li_;
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const MachineLoopInfo* loopInfo;
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AliasAnalysis *AA;
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BitVector allocatableRegs_;
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DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
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/// JoinedCopies - Keep track of copies eliminated due to coalescing.
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///
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SmallPtrSet<MachineInstr*, 32> JoinedCopies;
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/// ReMatCopies - Keep track of copies eliminated due to remat.
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///
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SmallPtrSet<MachineInstr*, 32> ReMatCopies;
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/// ReMatDefs - Keep track of definition instructions which have
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/// been remat'ed.
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SmallPtrSet<MachineInstr*, 8> ReMatDefs;
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public:
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static char ID; // Pass identifcation, replacement for typeid
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SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
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struct InstrSlots {
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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NUM = 4
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};
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};
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
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// This runs as an independent pass, so don't do anything.
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return false;
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}
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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private:
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/// joinIntervals - join compatible live intervals
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void joinIntervals();
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/// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
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/// copies that cannot yet be coalesced into the "TryAgain" list.
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void CopyCoalesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> &TryAgain);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coalesced away. If it is not currently
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/// possible to coalesce this interval, but it may be possible if other
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/// things get coalesced, then it returns true by reference in 'Again'.
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bool JoinCopy(CopyRec &TheCopy, bool &Again);
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/// JoinIntervals - Attempt to join these two intervals. On failure, this
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/// returns false. The output "SrcInt" will not have been modified, so we can
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/// use this information below to update aliases.
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bool JoinIntervals(CoalescerPair &CP);
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/// Return true if the two specified registers belong to different register
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/// classes. The registers may be either phys or virt regs.
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bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
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/// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
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/// the source value number is defined by a copy from the destination reg
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/// see if we can merge these two destination reg valno# into a single
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/// value number, eliminating a copy.
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bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
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/// HasOtherReachingDefs - Return true if there are definitions of IntB
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/// other than BValNo val# that can reach uses of AValno val# of IntA.
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bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
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VNInfo *AValNo, VNInfo *BValNo);
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/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
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/// If the source value number is defined by a commutable instruction and
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/// its other operand is coalesced to the copy dest register, see if we
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/// can transform the copy into a noop by commuting the definition.
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bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
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/// TrimLiveIntervalToLastUse - If there is a last use in the same basic
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/// block as the copy instruction, trim the ive interval to the last use
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/// and return true.
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bool TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
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MachineBasicBlock *CopyMBB,
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LiveInterval &li, const LiveRange *LR);
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/// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
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/// computation, replace the copy by rematerialize the definition.
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bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
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unsigned DstSubIdx, MachineInstr *CopyMI);
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/// isWinToJoinCrossClass - Return true if it's profitable to coalesce
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/// two virtual registers from different register classes.
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bool isWinToJoinCrossClass(unsigned SrcReg,
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unsigned DstReg,
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const TargetRegisterClass *SrcRC,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *NewRC);
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// update the subregister number if it is not zero. If DstReg is a
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/// physical register and the existing subregister number of the def / use
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/// being updated is not zero, make sure to set it to the correct physical
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/// subregister.
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void UpdateRegDefsUses(const CoalescerPair &CP);
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/// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
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/// Return true if live interval is removed.
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bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
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/// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
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/// extended by a dead copy. Mark the last use (if any) of the val# as kill
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/// as ends the live range there. If there isn't another use, then this
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/// live range is dead. Return true if live interval is removed.
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bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
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/// RemoveDeadDef - If a def of a live interval is now determined dead,
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/// remove the val# it defines. If the live interval becomes empty, remove
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/// it as well.
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bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
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/// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
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/// VNInfo copy flag for DstReg and all aliases.
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void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
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/// lastRegisterUse - Returns the last use of the specific register between
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/// cycles Start and End or NULL if there are no uses.
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MachineOperand *lastRegisterUse(SlotIndex Start, SlotIndex End,
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unsigned Reg, SlotIndex &LastUseIdx) const;
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};
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} // End llvm namespace
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#endif
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