Chandler Carruth b3ce94707a [x86] Add AVX1 and AVX2 testing to all of the 128-bit shuffle test ... cases. While clearly we don't need the AVX vector width, these ISA extensions often cause us to select different instructions and we should cover them even with the narrow vector width. Also, while here, nuke the stress_test2 contents. There is no reason to try to FileCheck this entire body when it is mostly a test for successfully surviving the code generator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218710 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-30 22:16:23 +00:00
..
AArch64	Recommit r218010 [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ.	2014-09-30 19:59:35 +00:00
ARM	Fix swift-atomics testcase	2014-09-23 23:18:01 +00:00
CPP
Generic	Fix crash with an insertvalue that produces an empty object.	2014-09-20 00:10:47 +00:00
Hexagon	Add missing attributes !cmp.[eq,gt,gtu] instructions.	2014-09-25 13:09:54 +00:00
Inputs
Mips	Add numeric extend, trunctate to mips fast-isel	2014-09-30 16:30:13 +00:00
MSP430
NVPTX
PowerPC	Refactor reciprocal and reciprocal square root estimate into target-independent functions (part 2).	2014-09-26 23:01:47 +00:00
R600	R600/SI: Fix printing of clamp and omod	2014-09-30 19:49:48 +00:00
SPARC
SystemZ
Thumb	[Thumb] Make load/store optimizer less conservative.	2014-09-24 16:35:50 +00:00
Thumb2
X86	[x86] Add AVX1 and AVX2 testing to all of the 128-bit shuffle test	2014-09-30 22:16:23 +00:00
XCore