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https://github.com/c64scene-ar/llvm-6502.git
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8f78fa827e
Custom lower AND, OR, XOR bitwise operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60098 91177308-0d34-0410-b5e6-96231b3b80d8
702 lines
25 KiB
C++
702 lines
25 KiB
C++
//===-- PIC16ISelLowering.cpp - PIC16 DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PIC16 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pic16-lower"
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#include "PIC16ISelLowering.h"
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#include "PIC16TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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using namespace llvm;
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// PIC16TargetLowering Constructor.
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PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
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: TargetLowering(TM) {
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Subtarget = &TM.getSubtarget<PIC16Subtarget>();
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addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
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setShiftAmountType(MVT::i8);
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setShiftAmountFlavor(Extend);
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setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
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setOperationAction(ISD::LOAD, MVT::i8, Legal);
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setOperationAction(ISD::LOAD, MVT::i16, Custom);
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::i8, Legal);
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setOperationAction(ISD::STORE, MVT::i16, Custom);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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setOperationAction(ISD::ADDE, MVT::i8, Custom);
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setOperationAction(ISD::ADDC, MVT::i8, Custom);
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setOperationAction(ISD::SUBE, MVT::i8, Custom);
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setOperationAction(ISD::SUBC, MVT::i8, Custom);
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setOperationAction(ISD::ADD, MVT::i8, Legal);
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setOperationAction(ISD::ADD, MVT::i16, Custom);
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setOperationAction(ISD::OR, MVT::i8, Custom);
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setOperationAction(ISD::AND, MVT::i8, Custom);
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setOperationAction(ISD::XOR, MVT::i8, Custom);
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setOperationAction(ISD::SHL, MVT::i16, Custom);
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setOperationAction(ISD::SHL, MVT::i32, Custom);
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//setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
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setTruncStoreAction(MVT::i16, MVT::i8, Custom);
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// Now deduce the information based on the above mentioned
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// actions
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computeRegisterProperties();
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}
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const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return NULL;
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case PIC16ISD::Lo: return "PIC16ISD::Lo";
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case PIC16ISD::Hi: return "PIC16ISD::Hi";
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case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
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case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
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case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
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case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
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case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
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case PIC16ISD::BCF: return "PIC16ISD::BCF";
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case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
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case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
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case PIC16ISD::RLF: return "PIC16ISD::RLF";
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case PIC16ISD::RRF: return "PIC16ISD::RRF";
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case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
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}
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}
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SDNode *PIC16TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
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switch (N->getOpcode()) {
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case ISD::GlobalAddress:
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return ExpandGlobalAddress(N, DAG);
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case ISD::STORE:
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return ExpandStore(N, DAG);
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case ISD::LOAD:
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return ExpandLoad(N, DAG);
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case ISD::ADD:
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return ExpandAdd(N, DAG);
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case ISD::SHL:
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return ExpandShift(N, DAG);
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default:
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assert (0 && "not implemented");
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}
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}
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SDNode *PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
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StoreSDNode *St = cast<StoreSDNode>(N);
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SDValue Chain = St->getChain();
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SDValue Src = St->getValue();
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SDValue Ptr = St->getBasePtr();
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MVT ValueType = Src.getValueType();
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unsigned StoreOffset = 0;
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SDValue PtrLo, PtrHi;
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LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset);
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if (ValueType == MVT::i8) {
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SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, MVT::Other, Chain, Src,
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PtrLo, PtrHi, DAG.getConstant (0, MVT::i8));
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return Store.getNode();
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}
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else if (ValueType == MVT::i16) {
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// Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
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SDValue SrcLo, SrcHi;
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GetExpandedParts(Src, DAG, SrcLo, SrcHi);
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SDValue ChainLo = Chain, ChainHi = Chain;
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if (Chain.getOpcode() == ISD::TokenFactor) {
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ChainLo = Chain.getOperand(0);
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ChainHi = Chain.getOperand(1);
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}
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SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other,
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ChainLo,
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SrcLo, PtrLo, PtrHi,
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DAG.getConstant (0 + StoreOffset, MVT::i8));
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SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi,
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SrcHi, PtrLo, PtrHi,
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DAG.getConstant (1 + StoreOffset, MVT::i8));
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return DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1),
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getChain(Store2)).getNode();
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}
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else if (ValueType == MVT::i32) {
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// Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
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SDValue SrcLo, SrcHi;
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GetExpandedParts(Src, DAG, SrcLo, SrcHi);
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// Get the expanded parts of each of SrcLo and SrcHi.
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SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
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GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
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GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
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SDValue ChainLo = Chain, ChainHi = Chain;
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if (Chain.getOpcode() == ISD::TokenFactor) {
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ChainLo = Chain.getOperand(0);
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ChainHi = Chain.getOperand(1);
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}
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SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
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ChainHi2 = ChainHi;
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if (ChainLo.getOpcode() == ISD::TokenFactor) {
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ChainLo1 = ChainLo.getOperand(0);
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ChainLo2 = ChainLo.getOperand(1);
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}
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if (ChainHi.getOpcode() == ISD::TokenFactor) {
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ChainHi1 = ChainHi.getOperand(0);
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ChainHi2 = ChainHi.getOperand(1);
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}
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SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other,
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ChainLo1,
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SrcLo1, PtrLo, PtrHi,
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DAG.getConstant (0 + StoreOffset, MVT::i8));
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SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainLo2,
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SrcLo2, PtrLo, PtrHi,
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DAG.getConstant (1 + StoreOffset, MVT::i8));
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SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi1,
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SrcHi1, PtrLo, PtrHi,
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DAG.getConstant (2 + StoreOffset, MVT::i8));
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SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi2,
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SrcHi2, PtrLo, PtrHi,
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DAG.getConstant (3 + StoreOffset, MVT::i8));
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SDValue RetLo = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1),
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getChain(Store2));
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SDValue RetHi = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store3),
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getChain(Store4));
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return DAG.getNode(ISD::TokenFactor, MVT::Other, RetLo, RetHi).getNode();
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}
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else {
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assert (0 && "value type not supported");
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}
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}
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// ExpandGlobalAddress -
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SDNode *PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
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GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
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SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
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G->getOffset());
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SDValue Lo = DAG.getNode(PIC16ISD::Lo, MVT::i8, TGA);
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SDValue Hi = DAG.getNode(PIC16ISD::Hi, MVT::i8, TGA);
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SDValue BP = DAG.getNode(ISD::BUILD_PAIR, MVT::i16, Lo, Hi);
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return BP.getNode();
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}
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bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
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assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
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if (Op.getOpcode() == ISD::BUILD_PAIR) {
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if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
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return true;
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}
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return false;
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}
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// Return true if DirectAddress is in ROM_SPACE
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bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
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// RomAddress is a GlobalAddress in ROM_SPACE_
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// If the Op is not a GlobalAddress return NULL without checking
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// anything further.
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if (!isDirectAddress(Op))
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return false;
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// Its a GlobalAddress.
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// It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
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SDValue TGA = Op.getOperand(0).getOperand(0);
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GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
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const Type *ValueType = GSDN->getGlobal()->getType();
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if (!isa<PointerType>(ValueType)) {
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assert(0 && "TGA must be of a PointerType");
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}
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int AddrSpace = dyn_cast<PointerType>(ValueType)->getAddressSpace();
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if (AddrSpace == PIC16ISD::ROM_SPACE)
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return true;
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// Any other address space return it false
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return false;
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}
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// To extract chain value from the SDValue Nodes
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// This function will help to maintain the chain extracting
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// code at one place. In case of any change in future it will
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// help maintain the code.
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SDValue PIC16TargetLowering::getChain(SDValue &Op) {
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SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
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// All nodes may not produce a chain. Therefore following assert
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// verifies that the node is returning a chain only.
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assert (Chain.getValueType() == MVT::Other && "Node does not have a chain");
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return Chain;
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}
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void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
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SDValue &Lo, SDValue &Hi) {
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SDNode *N = Op.getNode();
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unsigned NumValues = N->getNumValues();
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std::vector<MVT> VTs;
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MVT NewVT;
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std::vector<SDValue> Opers;
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// EXTRACT_ELEMENT should have same number and type of values that the
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// node replacing the EXTRACT_ELEMENT should have. (i.e. extracted element)
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// Some nodes such as LOAD and PIC16Load have more than one values. In such
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// cases EXTRACT_ELEMENT should have more than one values. Therefore creating
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// vector of Values for EXTRACT_ELEMENT. This list will have same number of
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// values as the extracted element will have.
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for (unsigned i=0;i < NumValues; ++i) {
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NewVT = getTypeToTransformTo(N->getValueType(i));
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VTs.push_back(NewVT);
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}
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// extract the lo component
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Opers.push_back(Op);
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Opers.push_back(DAG.getConstant(0,MVT::i8));
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Lo = DAG.getNode(ISD::EXTRACT_ELEMENT,VTs,&Opers[0],Opers.size());
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// extract the hi component
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Opers.clear();
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Opers.push_back(Op);
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Opers.push_back(DAG.getConstant(1,MVT::i8));
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Hi = DAG.getNode(ISD::EXTRACT_ELEMENT,VTs,&Opers[0],Opers.size());
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}
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// This function legalizes the PIC16 Addresses. If the Pointer is
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// -- Direct address variable residing
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// --> then a Banksel for that variable will be created.
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// -- Rom variable
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// --> then it will be treated as an indirect address.
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// -- Indirect address
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// --> then the address will be loaded into FSR
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// -- ADD with constant operand
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// --> then constant operand of ADD will be returned as Offset
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// and non-constant operand of ADD will be treated as pointer.
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// Returns the high and lo part of the address, and the offset(in case of ADD).
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void PIC16TargetLowering:: LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
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SDValue &Lo, SDValue &Hi,
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unsigned &Offset) {
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// Offset, by default, should be 0
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Offset = 0;
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// If the pointer is ADD with constant,
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// return the constant value as the offset
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if (Ptr.getOpcode() == ISD::ADD) {
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SDValue OperLeft = Ptr.getOperand(0);
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SDValue OperRight = Ptr.getOperand(1);
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if (OperLeft.getOpcode() == ISD::Constant) {
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Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
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Ptr = OperRight;
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} else {
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Ptr = OperLeft;
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Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
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}
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}
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if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
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// Direct addressing case for RAM variables. The Hi part is constant
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// and the Lo part is the TGA itself.
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Lo = Ptr.getOperand(0).getOperand(0);
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// For direct addresses Hi is a constant. Value 1 for the constant
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// signifies that banksel needs to generated for it. Value 0 for
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// the constant signifies that banksel does not need to be generated
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// for it. Mark it as 1 now and optimize later.
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Hi = DAG.getConstant(1, MVT::i8);
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return;
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}
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// Indirect addresses. Get the hi and lo parts of ptr.
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GetExpandedParts(Ptr, DAG, Lo, Hi);
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// Put the hi and lo parts into FSR.
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Lo = DAG.getNode(PIC16ISD::MTLO, MVT::i8, Lo);
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Hi = DAG.getNode(PIC16ISD::MTHI, MVT::i8, Hi);
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return;
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}
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SDNode *PIC16TargetLowering::ExpandAdd(SDNode *N, SelectionDAG &DAG) {
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SDValue OperLeft = N->getOperand(0);
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SDValue OperRight = N->getOperand(1);
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if((OperLeft.getOpcode() == ISD::Constant) ||
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(OperRight.getOpcode() == ISD::Constant)) {
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return NULL;
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}
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// These case are yet to be handled
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return NULL;
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}
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SDNode *PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
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LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
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SDValue Chain = LD->getChain();
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SDValue Ptr = LD->getBasePtr();
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SDValue Load, Offset;
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SDVTList Tys;
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MVT VT, NewVT;
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SDValue PtrLo, PtrHi;
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unsigned LoadOffset;
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// Legalize direct/indirect addresses. This will give the lo and hi parts
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// of the address and the offset.
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LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset);
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// Load from the pointer (direct address or FSR)
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VT = N->getValueType(0);
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unsigned NumLoads = VT.getSizeInBits() / 8;
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std::vector<SDValue> PICLoads;
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unsigned iter;
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MVT MemVT = LD->getMemoryVT();
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if(ISD::isNON_EXTLoad(N)) {
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for (iter=0; iter<NumLoads ; ++iter) {
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// Add the pointer offset if any
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Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
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Tys = DAG.getVTList(MVT::i8, MVT::Other);
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Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Chain, PtrLo, PtrHi,
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Offset);
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PICLoads.push_back(Load);
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}
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} else {
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// If it is extended load then use PIC16Load for Memory Bytes
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// and for all extended bytes perform action based on type of
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// extention - i.e. SignExtendedLoad or ZeroExtendedLoad
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// For extended loads this is the memory value type
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// i.e. without any extension
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MVT MemVT = LD->getMemoryVT();
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unsigned MemBytes = MemVT.getSizeInBits() / 8;
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unsigned ExtdBytes = VT.getSizeInBits() / 8;
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Offset = DAG.getConstant(LoadOffset, MVT::i8);
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Tys = DAG.getVTList(MVT::i8, MVT::Other);
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// For MemBytes generate PIC16Load with proper offset
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for (iter=0; iter<MemBytes; ++iter) {
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// Add the pointer offset if any
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Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
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Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Chain, PtrLo, PtrHi,
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Offset);
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PICLoads.push_back(Load);
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}
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// For SignExtendedLoad
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if (ISD::isSEXTLoad(N)) {
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// For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
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// highest MemByte
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SDValue SRA = DAG.getNode(ISD::SRA, MVT::i8, Load,
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DAG.getConstant(7, MVT::i8));
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for (iter=MemBytes; iter<ExtdBytes; ++iter) {
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PICLoads.push_back(SRA);
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}
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} else if (ISD::isZEXTLoad(N)) {
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// ZeroExtendedLoad -- For all ExtdBytes use constant 0
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SDValue ConstZero = DAG.getConstant(0, MVT::i8);
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for (iter=MemBytes; iter<ExtdBytes; ++iter) {
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PICLoads.push_back(ConstZero);
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}
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}
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}
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SDValue BP;
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if (VT == MVT::i8) {
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// Operand of Load is illegal -- Load itself is legal
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return PICLoads[0].getNode();
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}
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else if (VT == MVT::i16) {
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BP = DAG.getNode(ISD::BUILD_PAIR, VT, PICLoads[0], PICLoads[1]);
|
|
if (MemVT == MVT::i8)
|
|
Chain = getChain(PICLoads[0]);
|
|
else
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(PICLoads[0]),
|
|
getChain(PICLoads[1]));
|
|
} else if (VT == MVT::i32) {
|
|
SDValue BPs[2];
|
|
BPs[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i16, PICLoads[0], PICLoads[1]);
|
|
BPs[1] = DAG.getNode(ISD::BUILD_PAIR, MVT::i16, PICLoads[2], PICLoads[3]);
|
|
BP = DAG.getNode(ISD::BUILD_PAIR, VT, BPs[0], BPs[1]);
|
|
if (MemVT == MVT::i8)
|
|
Chain = getChain(PICLoads[0]);
|
|
else if (MemVT == MVT::i16)
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(PICLoads[0]),
|
|
getChain(PICLoads[1]));
|
|
else {
|
|
SDValue Chains[2];
|
|
Chains[0] = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
getChain(PICLoads[0]), getChain(PICLoads[1]));
|
|
Chains[1] = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
getChain(PICLoads[2]), getChain(PICLoads[3]));
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Chains[0], Chains[1]);
|
|
}
|
|
}
|
|
Tys = DAG.getVTList(VT, MVT::Other);
|
|
SDValue MergeV = DAG.getNode(ISD::MERGE_VALUES, Tys, BP, Chain);
|
|
return MergeV.getNode();
|
|
|
|
}
|
|
|
|
SDNode *PIC16TargetLowering::ExpandShift(SDNode *N, SelectionDAG &DAG) {
|
|
SDValue Value = N->getOperand(0);
|
|
SDValue Amt = N->getOperand(1);
|
|
SDValue BCF, BCFInput;
|
|
SDVTList Tys;
|
|
SDValue ShfCom; // Shift Component - Lo component should be shifted
|
|
SDValue RotCom; // Rotate Component- Hi component should be rotated
|
|
PIC16ISD::NodeType ShfNode, RotNode;
|
|
|
|
// Currently handling Constant shift only
|
|
if (Amt.getOpcode() != ISD::Constant)
|
|
return NULL;
|
|
|
|
// Following code considers 16 bit left-shift only
|
|
if (N->getValueType(0) != MVT::i16)
|
|
return NULL;
|
|
|
|
if (N->getOpcode() == ISD::SHL) {
|
|
ShfNode = PIC16ISD::LSLF;
|
|
RotNode = PIC16ISD::RLF;
|
|
} else if (N->getOpcode() == ISD::SRL) {
|
|
ShfNode = PIC16ISD::LRLF;
|
|
RotNode = PIC16ISD::RRF;
|
|
}
|
|
unsigned ShiftAmt = dyn_cast<ConstantSDNode>(Amt)->getZExtValue();
|
|
SDValue StatusReg = DAG.getRegister(PIC16::STATUS, MVT::i8);
|
|
// 0th Bit in StatusReg is CarryBit
|
|
SDValue CarryBit= DAG.getConstant(0, MVT::i8);
|
|
|
|
GetExpandedParts(Value, DAG, ShfCom, RotCom);
|
|
BCFInput = DAG.getNode(PIC16ISD::Dummy, MVT::Flag);
|
|
Tys = DAG.getVTList(MVT::i8, MVT::Flag);
|
|
|
|
for (unsigned i=0;i<ShiftAmt;i++) {
|
|
BCF = DAG.getNode(PIC16ISD::BCF, MVT::Flag, StatusReg, CarryBit, BCFInput);
|
|
|
|
// Following are Two-Address Instructions
|
|
ShfCom = DAG.getNode(ShfNode, Tys, ShfCom, BCF);
|
|
RotCom = DAG.getNode(RotNode, Tys, RotCom, ShfCom.getValue(1));
|
|
|
|
BCFInput = RotCom.getValue(1);
|
|
}
|
|
|
|
SDValue BP = DAG.getNode(ISD::BUILD_PAIR, N->getValueType(0), ShfCom, RotCom);
|
|
return BP.getNode();
|
|
}
|
|
|
|
SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
|
|
switch (Op.getOpcode()) {
|
|
case ISD::FORMAL_ARGUMENTS:
|
|
return LowerFORMAL_ARGUMENTS(Op, DAG);
|
|
case ISD::ADDC:
|
|
return LowerADDC(Op, DAG);
|
|
case ISD::ADDE:
|
|
return LowerADDE(Op, DAG);
|
|
case ISD::SUBE:
|
|
return LowerSUBE(Op, DAG);
|
|
case ISD::SUBC:
|
|
return LowerSUBC(Op, DAG);
|
|
case ISD::LOAD:
|
|
return SDValue(ExpandLoad(Op.getNode(), DAG), Op.getResNo());
|
|
case ISD::STORE:
|
|
return SDValue(ExpandStore(Op.getNode(), DAG), Op.getResNo());
|
|
case ISD::SHL:
|
|
return SDValue(ExpandShift(Op.getNode(), DAG), Op.getResNo());
|
|
case ISD::OR:
|
|
case ISD::AND:
|
|
case ISD::XOR:
|
|
return LowerBinOp(Op, DAG);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
|
|
assert (Op.getValueType() == MVT::i8
|
|
&& "illegal value type to store on stack.");
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
const Function *Func = MF.getFunction();
|
|
const std::string FuncName = Func->getName();
|
|
|
|
char *tmpName = new char [strlen(FuncName.c_str()) + 6];
|
|
|
|
// Put the value on stack.
|
|
// Get a stack slot index and convert to es.
|
|
int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
|
|
sprintf(tmpName, "%s.tmp", FuncName.c_str());
|
|
SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
|
|
|
|
// Store the value to ES.
|
|
SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, MVT::Other,
|
|
DAG.getEntryNode(),
|
|
Op, ES,
|
|
DAG.getConstant (1, MVT::i8), // Banksel.
|
|
DAG.getConstant (FI, MVT::i8));
|
|
|
|
// Load the value from ES.
|
|
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
|
|
SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Store,
|
|
ES, DAG.getConstant (1, MVT::i8),
|
|
DAG.getConstant (FI, MVT::i8));
|
|
|
|
return Load.getValue(0);
|
|
}
|
|
|
|
SDValue PIC16TargetLowering:: LowerBinOp(SDValue Op, SelectionDAG &DAG) {
|
|
// We should have handled larger operands in type legalizer itself.
|
|
assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
|
|
|
|
// Return the original Op if the one of the operands is already a load.
|
|
if (Op.getOperand(0).getOpcode() == PIC16ISD::PIC16Load
|
|
|| Op.getOperand(1).getOpcode() == PIC16ISD::PIC16Load)
|
|
return Op;
|
|
|
|
// Put one value on stack.
|
|
SDValue NewVal = ConvertToMemOperand (Op.getOperand(1), DAG);
|
|
|
|
return DAG.getNode(Op.getOpcode(), MVT::i8, Op.getOperand(0), NewVal);
|
|
}
|
|
|
|
SDValue PIC16TargetLowering:: LowerADDC(SDValue Op, SelectionDAG &DAG) {
|
|
// We should have handled larger operands in type legalizer itself.
|
|
assert (Op.getValueType() == MVT::i8 && "illegal addc to lower");
|
|
|
|
// Nothing to do if the one of the operands is already a load.
|
|
if (Op.getOperand(0).getOpcode() == PIC16ISD::PIC16Load
|
|
|| Op.getOperand(1).getOpcode() == PIC16ISD::PIC16Load)
|
|
return SDValue();
|
|
|
|
// Put one value on stack.
|
|
SDValue NewVal = ConvertToMemOperand (Op.getOperand(1), DAG);
|
|
|
|
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
|
|
return DAG.getNode(ISD::ADDC, Tys, Op.getOperand(0), NewVal);
|
|
}
|
|
|
|
SDValue PIC16TargetLowering:: LowerADDE(SDValue Op, SelectionDAG &DAG) {
|
|
// We should have handled larger operands in type legalizer itself.
|
|
assert (Op.getValueType() == MVT::i8 && "illegal adde to lower");
|
|
|
|
// Nothing to do if the one of the operands is already a load.
|
|
if (Op.getOperand(0).getOpcode() == PIC16ISD::PIC16Load
|
|
|| Op.getOperand(1).getOpcode() == PIC16ISD::PIC16Load)
|
|
return SDValue();
|
|
|
|
// Put one value on stack.
|
|
SDValue NewVal = ConvertToMemOperand (Op.getOperand(1), DAG);
|
|
|
|
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
|
|
return DAG.getNode(ISD::ADDE, Tys, Op.getOperand(0), NewVal,
|
|
Op.getOperand(2));
|
|
}
|
|
|
|
SDValue PIC16TargetLowering:: LowerSUBC(SDValue Op, SelectionDAG &DAG) {
|
|
// We should have handled larger operands in type legalizer itself.
|
|
assert (Op.getValueType() == MVT::i8 && "illegal subc to lower");
|
|
|
|
// Nothing to do if the first operand is already a load.
|
|
if (Op.getOperand(0).getOpcode() == PIC16ISD::PIC16Load)
|
|
return SDValue();
|
|
|
|
// Put first operand on stack.
|
|
SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG);
|
|
|
|
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
|
|
return DAG.getNode(ISD::SUBC, Tys, NewVal, Op.getOperand(1));
|
|
}
|
|
|
|
SDValue PIC16TargetLowering:: LowerSUBE(SDValue Op, SelectionDAG &DAG) {
|
|
// We should have handled larger operands in type legalizer itself.
|
|
assert (Op.getValueType() == MVT::i8 && "illegal sube to lower");
|
|
|
|
// Nothing to do if the first operand is already a load.
|
|
if (Op.getOperand(0).getOpcode() == PIC16ISD::PIC16Load)
|
|
return SDValue();
|
|
|
|
// Put first operand on stack.
|
|
SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG);
|
|
|
|
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
|
|
return DAG.getNode(ISD::SUBE, Tys, NewVal, Op.getOperand(1),
|
|
Op.getOperand(2));
|
|
}
|
|
|
|
// LowerFORMAL_ARGUMENTS - In Lowering FORMAL ARGUMENTS - MERGE_VALUES nodes
|
|
// is returned. MERGE_VALUES nodes number of operands and number of values are
|
|
// equal. Therefore to construct MERGE_VALUE node, UNDEF nodes equal to the
|
|
// number of arguments of function have been created.
|
|
|
|
SDValue PIC16TargetLowering:: LowerFORMAL_ARGUMENTS(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
SmallVector<SDValue, 8> ArgValues;
|
|
unsigned NumArgs = Op.getNumOperands() - 3;
|
|
|
|
// Creating UNDEF nodes to meet the requirement of MERGE_VALUES node.
|
|
for(unsigned i = 0 ; i<NumArgs ; i++) {
|
|
SDValue TempNode = DAG.getNode(ISD::UNDEF, Op.getNode()->getValueType(i));
|
|
ArgValues.push_back(TempNode);
|
|
}
|
|
|
|
ArgValues.push_back(Op.getOperand(0));
|
|
return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
|
|
&ArgValues[0],
|
|
ArgValues.size()).getValue(Op.getResNo());
|
|
}
|
|
|
|
// Perform DAGCombine of PIC16Load
|
|
SDValue PIC16TargetLowering::
|
|
PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
SDValue Chain = N->getOperand(0);
|
|
if (N->hasNUsesOfValue(0, 0)) {
|
|
DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
|
|
SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
|
|
DAGCombinerInfo &DCI) const {
|
|
switch (N->getOpcode()) {
|
|
case PIC16ISD::PIC16Load:
|
|
return PerformPIC16LoadCombine(N, DCI);
|
|
}
|
|
return SDValue();
|
|
}
|