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The previous implementation was extending the live range of SGPRs by modifying the live intervals directly. This was causing a lot of machine verification errors when the machine scheduler was enabled. The new implementation adds pseudo instructions with implicit uses to extend the live ranges of SGPRs, which works much better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218351 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
6.4 KiB
C++
192 lines
6.4 KiB
C++
//===-- SIFixSGPRLiveRanges.cpp - Fix SGPR live ranges ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// SALU instructions ignore control flow, so we need to modify the live ranges
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/// of the registers they define in some cases.
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///
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/// The main case we need to handle is when a def is used in one side of a
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/// branch and not another. For example:
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///
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/// %def
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/// IF
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/// ...
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/// ...
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/// ELSE
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/// %use
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/// ...
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/// ENDIF
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///
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/// Here we need the register allocator to avoid assigning any of the defs
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/// inside of the IF to the same register as %def. In traditional live
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/// interval analysis %def is not live inside the IF branch, however, since
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/// SALU instructions inside of IF will be executed even if the branch is not
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/// taken, there is the chance that one of the instructions will overwrite the
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/// value of %def, so the use in ELSE will see the wrong value.
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///
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/// The strategy we use for solving this is to add an extra use after the ENDIF:
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///
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/// %def
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/// IF
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/// ...
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/// ...
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/// ELSE
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/// %use
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/// ...
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/// ENDIF
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/// %use
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///
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/// Adding this use will make the def live thoughout the IF branch, which is
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/// what we want.
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#include "AMDGPU.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-fix-sgpr-live-ranges"
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namespace {
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class SIFixSGPRLiveRanges : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIFixSGPRLiveRanges() : MachineFunctionPass(ID) {
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initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI Fix SGPR live ranges";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.addRequired<MachinePostDominatorTree>();
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIFixSGPRLiveRanges, DEBUG_TYPE,
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"SI Fix SGPR Live Ranges", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
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INITIALIZE_PASS_END(SIFixSGPRLiveRanges, DEBUG_TYPE,
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"SI Fix SGPR Live Ranges", false, false)
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char SIFixSGPRLiveRanges::ID = 0;
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char &llvm::SIFixSGPRLiveRangesID = SIFixSGPRLiveRanges::ID;
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FunctionPass *llvm::createSIFixSGPRLiveRangesPass() {
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return new SIFixSGPRLiveRanges();
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}
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bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
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MF.getSubtarget().getRegisterInfo());
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LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
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MachinePostDominatorTree *PDT = &getAnalysis<MachinePostDominatorTree>();
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std::vector<std::pair<unsigned, LiveRange *>> SGPRLiveRanges;
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// First pass, collect all live intervals for SGPRs
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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for (const MachineOperand &MO : MI.defs()) {
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if (MO.isImplicit())
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continue;
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unsigned Def = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Def)) {
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if (TRI->isSGPRClass(MRI.getRegClass(Def)))
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SGPRLiveRanges.push_back(
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std::make_pair(Def, &LIS->getInterval(Def)));
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} else if (TRI->isSGPRClass(TRI->getPhysRegClass(Def))) {
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SGPRLiveRanges.push_back(
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std::make_pair(Def, &LIS->getRegUnit(Def)));
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}
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}
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}
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}
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// Second pass fix the intervals
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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if (MBB.succ_size() < 2)
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continue;
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// We have structured control flow, so number of succesors should be two.
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assert(MBB.succ_size() == 2);
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MachineBasicBlock *SuccA = *MBB.succ_begin();
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MachineBasicBlock *SuccB = *(++MBB.succ_begin());
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MachineBasicBlock *NCD = PDT->findNearestCommonDominator(SuccA, SuccB);
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if (!NCD)
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continue;
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MachineBasicBlock::iterator NCDTerm = NCD->getFirstTerminator();
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if (NCDTerm != NCD->end() && NCDTerm->getOpcode() == AMDGPU::SI_ELSE) {
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assert(NCD->succ_size() == 2);
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// We want to make sure we insert the Use after the ENDIF, not after
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// the ELSE.
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NCD = PDT->findNearestCommonDominator(*NCD->succ_begin(),
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*(++NCD->succ_begin()));
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}
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assert(SuccA && SuccB);
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for (std::pair<unsigned, LiveRange*> RegLR : SGPRLiveRanges) {
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unsigned Reg = RegLR.first;
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LiveRange *LR = RegLR.second;
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// FIXME: We could be smarter here. If the register is Live-In to
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// one block, but the other doesn't have any SGPR defs, then there
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// won't be a conflict. Also, if the branch decision is based on
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// a value in an SGPR, then there will be no conflict.
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bool LiveInToA = LIS->isLiveInToMBB(*LR, SuccA);
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bool LiveInToB = LIS->isLiveInToMBB(*LR, SuccB);
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if ((!LiveInToA && !LiveInToB) ||
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(LiveInToA && LiveInToB))
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continue;
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// This interval is live in to one successor, but not the other, so
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// we need to update its range so it is live in to both.
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DEBUG(dbgs() << "Possible SGPR conflict detected " << " in " << *LR <<
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" BB#" << SuccA->getNumber() << ", BB#" <<
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SuccB->getNumber() <<
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" with NCD = " << NCD->getNumber() << '\n');
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// FIXME: Need to figure out how to update LiveRange here so this pass
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// will be able to preserve LiveInterval analysis.
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BuildMI(*NCD, NCD->getFirstNonPHI(), DebugLoc(),
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TII->get(AMDGPU::SGPR_USE))
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.addReg(Reg, RegState::Implicit);
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DEBUG(NCD->getFirstNonPHI()->dump());
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}
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}
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return false;
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}
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