mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
70cd88fb7b
that have that constraint. This is currently just assigning a fixed set of registers, and it only handles VLDn for n=2,3,4 with DPR registers. I'm going to expand it to handle more operations next; we can make it smarter once everything is working correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
1.0 KiB
CMake
38 lines
1.0 KiB
CMake
set(LLVM_TARGET_DEFINITIONS ARM.td)
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tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(ARMGenRegisterNames.inc -gen-register-enums)
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tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
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tablegen(ARMGenInstrNames.inc -gen-instr-enums)
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tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
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tablegen(ARMGenCodeEmitter.inc -gen-emitter)
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tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
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tablegen(ARMGenDAGISel.inc -gen-dag-isel)
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tablegen(ARMGenCallingConv.inc -gen-callingconv)
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tablegen(ARMGenSubtarget.inc -gen-subtarget)
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add_llvm_target(ARMCodeGen
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ARMBaseInstrInfo.cpp
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ARMBaseRegisterInfo.cpp
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ARMCodeEmitter.cpp
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ARMConstantIslandPass.cpp
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ARMConstantPoolValue.cpp
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ARMInstrInfo.cpp
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ARMISelDAGToDAG.cpp
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ARMISelLowering.cpp
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ARMJITInfo.cpp
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ARMLoadStoreOptimizer.cpp
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ARMRegisterInfo.cpp
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ARMSubtarget.cpp
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ARMTargetAsmInfo.cpp
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ARMTargetMachine.cpp
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NEONPreAllocPass.cpp
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Thumb1InstrInfo.cpp
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Thumb1RegisterInfo.cpp
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Thumb2ITBlockPass.cpp
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Thumb2InstrInfo.cpp
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Thumb2RegisterInfo.cpp
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)
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target_link_libraries (LLVMARMCodeGen LLVMSelectionDAG)
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