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2fbfdcffd3
class. The Method class is obsolete (renamed) and all references to it are being converted over to Function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2144 91177308-0d34-0410-b5e6-96231b3b80d8
363 lines
12 KiB
C++
363 lines
12 KiB
C++
#include "llvm/CodeGen/LiveRangeInfo.h"
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#include "llvm/CodeGen/RegClass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/BasicBlock.h"
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#include "Support/SetOperations.h"
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#include <iostream>
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using std::cerr;
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LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
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std::vector<RegClass *> &RCL)
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: Meth(F), TM(tm), RegClassList(RCL), MRI(tm.getRegInfo()) { }
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LiveRangeInfo::~LiveRangeInfo() {
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for (LiveRangeMapType::iterator MI = LiveRangeMap.begin();
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MI != LiveRangeMap.end(); ++MI) {
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if (MI->first && MI->second) {
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LiveRange *LR = MI->second;
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// we need to be careful in deleting LiveRanges in LiveRangeMap
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// since two/more Values in the live range map can point to the same
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// live range. We have to make the other entries NULL when we delete
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// a live range.
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for(LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
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LiveRangeMap[*LI] = 0;
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delete LR;
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}
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}
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}
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//---------------------------------------------------------------------------
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// union two live ranges into one. The 2nd LR is deleted. Used for coalescing.
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// Note: the caller must make sure that L1 and L2 are distinct and both
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// LRs don't have suggested colors
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//---------------------------------------------------------------------------
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void LiveRangeInfo::unionAndUpdateLRs(LiveRange *L1, LiveRange *L2) {
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assert(L1 != L2 && (!L1->hasSuggestedColor() || !L2->hasSuggestedColor()));
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set_union(*L1, *L2); // add elements of L2 to L1
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for(ValueSet::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) {
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//assert(( L1->getTypeID() == L2->getTypeID()) && "Merge:Different types");
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L1->insert(*L2It); // add the var in L2 to L1
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LiveRangeMap[*L2It] = L1; // now the elements in L2 should map
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//to L1
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}
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// Now if LROfDef(L1) has a suggested color, it will remain.
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// But, if LROfUse(L2) has a suggested color, the new range
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// must have the same color.
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if(L2->hasSuggestedColor())
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L1->setSuggestedColor(L2->getSuggestedColor());
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if (L2->isCallInterference())
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L1->setCallInterference();
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// add the spill costs
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L1->addSpillCost(L2->getSpillCost());
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delete L2; // delete L2 as it is no longer needed
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}
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//---------------------------------------------------------------------------
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// Method for constructing all live ranges in a function. It creates live
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// ranges for all values defined in the instruction stream. Also, it
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// creates live ranges for all incoming arguments of the function.
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//---------------------------------------------------------------------------
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void LiveRangeInfo::constructLiveRanges() {
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if (DEBUG_RA)
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cerr << "Consturcting Live Ranges ...\n";
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// first find the live ranges for all incoming args of the function since
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// those LRs start from the start of the function
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// get the argument list
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const Function::ArgumentListType& ArgList = Meth->getArgumentList();
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Function::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
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LiveRange * ArgRange = new LiveRange(); // creates a new LR and
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const Value *Val = (const Value *) *ArgIt;
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ArgRange->insert(Val); // add the arg (def) to it
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LiveRangeMap[Val] = ArgRange;
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// create a temp machine op to find the register class of value
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//const MachineOperand Op(MachineOperand::MO_VirtualRegister);
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unsigned rcid = MRI.getRegClassIDOfValue( Val );
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ArgRange->setRegClass(RegClassList[ rcid ] );
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if( DEBUG_RA > 1) {
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cerr << " adding LiveRange for argument "
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<< RAV((const Value *)*ArgIt) << "\n";
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}
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}
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// Now suggest hardware registers for these function args
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MRI.suggestRegs4MethodArgs(Meth, *this);
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// Now find speical LLVM instructions (CALL, RET) and LRs in machine
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// instructions.
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//
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for (Function::const_iterator BBI = Meth->begin(); BBI != Meth->end(); ++BBI){
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// Now find all LRs for machine the instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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// iterate over all the machine instructions in BB
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for(MachineCodeForBasicBlock::const_iterator MInstIterator = MIVec.begin();
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MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr *MInst = *MInstIterator;
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// Now if the machine instruction is a call/return instruction,
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// add it to CallRetInstrList for processing its implicit operands
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if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
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TM.getInstrInfo().isCall(MInst->getOpCode()))
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CallRetInstrList.push_back( MInst );
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// iterate over MI operands to find defs
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for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
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OpE = MInst->end(); OpI != OpE; ++OpI) {
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if(DEBUG_RA) {
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MachineOperand::MachineOperandType OpTyp =
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OpI.getMachineOperand().getOperandType();
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if (OpTyp == MachineOperand::MO_CCRegister)
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cerr << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:"
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<< RAV(OpI.getMachineOperand().getVRegValue()) << "\n";
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}
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// create a new LR iff this operand is a def
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if (OpI.isDef()) {
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const Value *Def = *OpI;
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// Only instruction values are accepted for live ranges here
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if (Def->getValueType() != Value::InstructionVal ) {
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cerr << "\n**%%Error: Def is not an instruction val. Def="
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<< RAV(Def) << "\n";
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continue;
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}
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LiveRange *DefRange = LiveRangeMap[Def];
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// see LR already there (because of multiple defs)
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if( !DefRange) { // if it is not in LiveRangeMap
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DefRange = new LiveRange(); // creates a new live range and
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DefRange->insert(Def); // add the instruction (def) to it
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LiveRangeMap[ Def ] = DefRange; // update the map
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if (DEBUG_RA > 1)
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cerr << " creating a LR for def: " << RAV(Def) << "\n";
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// set the register class of the new live range
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//assert( RegClassList.size() );
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MachineOperand::MachineOperandType OpTy =
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OpI.getMachineOperand().getOperandType();
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bool isCC = ( OpTy == MachineOperand::MO_CCRegister);
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unsigned rcid = MRI.getRegClassIDOfValue(
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OpI.getMachineOperand().getVRegValue(), isCC );
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if (isCC && DEBUG_RA)
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cerr << "\a**created a LR for a CC reg:"
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<< RAV(OpI.getMachineOperand().getVRegValue());
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DefRange->setRegClass(RegClassList[rcid]);
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} else {
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DefRange->insert(Def); // add the opearand to def range
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// update the map - Operand points
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// to the merged set
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LiveRangeMap[Def] = DefRange;
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if (DEBUG_RA > 1)
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cerr << " added to an existing LR for def: "
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<< RAV(Def) << "\n";
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}
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} // if isDef()
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} // for all opereands in machine instructions
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} // for all machine instructions in the BB
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} // for all BBs in function
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// Now we have to suggest clors for call and return arg live ranges.
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// Also, if there are implicit defs (e.g., retun value of a call inst)
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// they must be added to the live range list
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suggestRegs4CallRets();
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if( DEBUG_RA)
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cerr << "Initial Live Ranges constructed!\n";
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}
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//---------------------------------------------------------------------------
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// If some live ranges must be colored with specific hardware registers
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// (e.g., for outgoing call args), suggesting of colors for such live
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// ranges is done using target specific function. Those functions are called
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// from this function. The target specific methods must:
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// 1) suggest colors for call and return args.
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// 2) create new LRs for implicit defs in machine instructions
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//---------------------------------------------------------------------------
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void LiveRangeInfo::suggestRegs4CallRets()
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{
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CallRetInstrListType::const_iterator It = CallRetInstrList.begin();
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for( ; It != CallRetInstrList.end(); ++It ) {
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const MachineInstr *MInst = *It;
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MachineOpCode OpCode = MInst->getOpCode();
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if( (TM.getInstrInfo()).isReturn(OpCode) )
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MRI.suggestReg4RetValue( MInst, *this);
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else if( (TM.getInstrInfo()).isCall( OpCode ) )
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MRI.suggestRegs4CallArgs( MInst, *this, RegClassList );
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else
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assert( 0 && "Non call/ret instr in CallRetInstrList" );
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}
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}
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//--------------------------------------------------------------------------
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// The following method coalesces live ranges when possible. This method
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// must be called after the interference graph has been constructed.
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/* Algorithm:
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for each BB in function
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for each machine instruction (inst)
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for each definition (def) in inst
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for each operand (op) of inst that is a use
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if the def and op are of the same register type
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if the def and op do not interfere //i.e., not simultaneously live
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if (degree(LR of def) + degree(LR of op)) <= # avail regs
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if both LRs do not have suggested colors
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merge2IGNodes(def, op) // i.e., merge 2 LRs
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*/
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//---------------------------------------------------------------------------
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void LiveRangeInfo::coalesceLRs()
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{
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if(DEBUG_RA)
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cerr << "\nCoalscing LRs ...\n";
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for(Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
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BBI != BBE; ++BBI) {
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr * MInst = *MInstIterator;
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if( DEBUG_RA > 1) {
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cerr << " *Iterating over machine instr ";
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MInst->dump();
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cerr << "\n";
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}
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// iterate over MI operands to find defs
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for(MachineInstr::const_val_op_iterator DefI = MInst->begin(),
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DefE = MInst->end(); DefI != DefE; ++DefI) {
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if (DefI.isDef()) { // iff this operand is a def
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LiveRange *LROfDef = getLiveRangeForValue( *DefI );
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RegClass *RCOfDef = LROfDef->getRegClass();
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MachineInstr::const_val_op_iterator UseI = MInst->begin(),
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UseE = MInst->end();
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for( ; UseI != UseE; ++UseI){ // for all uses
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LiveRange *LROfUse = getLiveRangeForValue( *UseI );
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if (!LROfUse) { // if LR of use is not found
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//don't warn about labels
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if (!isa<BasicBlock>(*UseI) && DEBUG_RA)
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cerr << " !! Warning: No LR for use " << RAV(*UseI) << "\n";
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continue; // ignore and continue
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}
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if (LROfUse == LROfDef) // nothing to merge if they are same
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continue;
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if (MRI.getRegType(LROfDef) == MRI.getRegType(LROfUse)) {
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// If the two RegTypes are the same
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if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
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unsigned CombinedDegree =
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LROfDef->getUserIGNode()->getNumOfNeighbors() +
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LROfUse->getUserIGNode()->getNumOfNeighbors();
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if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) {
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// if both LRs do not have suggested colors
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if (!(LROfDef->hasSuggestedColor() &&
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LROfUse->hasSuggestedColor())) {
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RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
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unionAndUpdateLRs(LROfDef, LROfUse);
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}
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} // if combined degree is less than # of regs
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} // if def and use do not interfere
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}// if reg classes are the same
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} // for all uses
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} // if def
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} // for all defs
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} // for all machine instructions
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} // for all BBs
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if (DEBUG_RA)
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cerr << "\nCoalscing Done!\n";
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}
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/*--------------------------- Debug code for printing ---------------*/
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void LiveRangeInfo::printLiveRanges() {
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LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator
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cerr << "\nPrinting Live Ranges from Hash Map:\n";
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for( ; HMI != LiveRangeMap.end(); ++HMI) {
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if (HMI->first && HMI->second) {
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cerr << " " << RAV(HMI->first) << "\t: ";
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printSet(*HMI->second); cerr << "\n";
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}
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}
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}
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