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https://github.com/c64scene-ar/llvm-6502.git
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8fc760cbe8
My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
243 lines
5.8 KiB
LLVM
243 lines
5.8 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Test sitofp
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define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ARM: sitofp_single_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i32 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ARM: sitofp_single_i16
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; ARM: sxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i16
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; THUMB: sxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i16 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ARM: sitofp_single_i8
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; ARM: sxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i8
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; THUMB: sxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i8 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i32 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i16
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; ARM: sxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i16
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; THUMB: sxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i16 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i8
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; ARM: sxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i8
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; THUMB: sxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i8 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test uitofp
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define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ARM: uitofp_single_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i32 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ARM: uitofp_single_i16
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; ARM: uxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i16
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; THUMB: uxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i16 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ARM: uitofp_single_i8
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; ARM: and r0, r0, #255
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i8
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; THUMB: and r0, r0, #255
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i8 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i32 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i16
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; ARM: uxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i16
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; THUMB: uxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i16 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i8
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; ARM: and r0, r0, #255
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i8
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; THUMB: and r0, r0, #255
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i8 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test fptosi
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define void @fptosi_float(float %a) nounwind ssp {
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entry:
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; ARM: fptosi_float
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; ARM: vcvt.s32.f32 s0, s0
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; THUMB: fptosi_float
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; THUMB: vcvt.s32.f32 s0, s0
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%b.addr = alloca i32, align 4
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%conv = fptosi float %a to i32
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store i32 %conv, i32* %b.addr, align 4
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ret void
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}
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define void @fptosi_double(double %a) nounwind ssp {
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entry:
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; ARM: fptosi_double
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; ARM: vcvt.s32.f64 s0, d16
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; THUMB: fptosi_double
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; THUMB: vcvt.s32.f64 s0, d16
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%b.addr = alloca i32, align 8
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%conv = fptosi double %a to i32
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store i32 %conv, i32* %b.addr, align 8
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ret void
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}
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; Test fptoui
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define void @fptoui_float(float %a) nounwind ssp {
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entry:
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; ARM: fptoui_float
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; ARM: vcvt.u32.f32 s0, s0
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; THUMB: fptoui_float
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; THUMB: vcvt.u32.f32 s0, s0
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%b.addr = alloca i32, align 4
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%conv = fptoui float %a to i32
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store i32 %conv, i32* %b.addr, align 4
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ret void
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}
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define void @fptoui_double(double %a) nounwind ssp {
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entry:
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; ARM: fptoui_double
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; ARM: vcvt.u32.f64 s0, d16
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; THUMB: fptoui_double
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; THUMB: vcvt.u32.f64 s0, d16
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%b.addr = alloca i32, align 8
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%conv = fptoui double %a to i32
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store i32 %conv, i32* %b.addr, align 8
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ret void
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}
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