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f0c1388dd1
Aside from a few minor latency corrections, the major change here is a new hazard recognizer which focuses on better dispatch-group formation on the POWER7. As with the PPC970's hazard recognizer, the most important thing it does is avoid load-after-store hazards within the same dispatch group. It uses the POWER7's special dispatch-group-terminating nop instruction (instead of inserting multiple regular nop instructions). This new hazard recognizer makes use of the scheduling dependency graph itself, built using AA information, to robustly detect the possibility of load-after-store hazards. significant test-suite performance changes (the error bars are 99.5% confidence intervals based on 5 test-suite runs both with and without the change -- speedups are negative): speedups: MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2 -0.55171% +/- 0.333168% MultiSource/Benchmarks/TSVC/CrossingThresholds-dbl/CrossingThresholds-dbl -17.5576% +/- 14.598% MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl -29.5708% +/- 7.09058% MultiSource/Benchmarks/TSVC/Reductions-flt/Reductions-flt -34.9471% +/- 11.4391% SingleSource/Benchmarks/BenchmarkGame/puzzle -25.1347% +/- 11.0104% SingleSource/Benchmarks/Misc/flops-8 -17.7297% +/- 9.79061% SingleSource/Benchmarks/Shootout-C++/ary3 -35.5018% +/- 23.9458% SingleSource/Regression/C/uint64_to_float -56.3165% +/- 25.4234% SingleSource/UnitTests/Vectorizer/gcc-loops -18.5309% +/- 6.8496% regressions: MultiSource/Benchmarks/ASCI_Purple/SMG2000/smg2000 18.351% +/- 12.156% SingleSource/Benchmarks/Shootout-C++/methcall 27.3086% +/- 14.4733% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197099 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
9.7 KiB
C++
236 lines
9.7 KiB
C++
//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC_INSTRUCTIONINFO_H
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#define POWERPC_INSTRUCTIONINFO_H
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#include "PPC.h"
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#include "PPCRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "PPCGenInstrInfo.inc"
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namespace llvm {
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/// PPCII - This namespace holds all of the PowerPC target-specific
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/// per-instruction flags. These must match the corresponding definitions in
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/// PPC.td and PPCInstrFormats.td.
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namespace PPCII {
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enum {
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// PPC970 Instruction Flags. These flags describe the characteristics of the
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// PowerPC 970 (aka G5) dispatch groups and how they are formed out of
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// raw machine instructions.
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/// PPC970_First - This instruction starts a new dispatch group, so it will
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/// always be the first one in the group.
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PPC970_First = 0x1,
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/// PPC970_Single - This instruction starts a new dispatch group and
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/// terminates it, so it will be the sole instruction in the group.
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PPC970_Single = 0x2,
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/// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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/// two dispatch pipes to be available to issue.
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PPC970_Cracked = 0x4,
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/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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/// an instruction is issued to.
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PPC970_Shift = 3,
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PPC970_Mask = 0x07 << PPC970_Shift
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};
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enum PPC970_Unit {
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/// These are the various PPC970 execution unit pipelines. Each instruction
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/// is one of these.
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PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
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PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
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PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
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PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
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PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
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PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
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PPC970_BRU = 7 << PPC970_Shift // Branch Unit
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};
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} // end namespace PPCII
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class PPCInstrInfo : public PPCGenInstrInfo {
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PPCTargetMachine &TM;
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const PPCRegisterInfo RI;
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bool StoreRegToStackSlot(MachineFunction &MF,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI, bool &SpillsVRS) const;
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bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI, bool &SpillsVRS) const;
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virtual void anchor();
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public:
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explicit PPCInstrInfo(PPCTargetMachine &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const;
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virtual
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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virtual
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const {
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return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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UseNode, UseIdx);
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}
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bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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// Select analysis.
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virtual bool canInsertSelect(const MachineBasicBlock&,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned, unsigned, int&, int&, int&) const;
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virtual void insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned TrueReg, unsigned FalseReg) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const;
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// If conversion by predication (only supported by some branch instructions).
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// All of the profitability checks always return true; it is always
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// profitable to use the predicated branches.
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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const BranchProbability &Probability) const {
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return true;
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}
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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const BranchProbability &Probability) const;
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virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles,
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const BranchProbability
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&Probability) const {
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return true;
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}
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virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const {
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return false;
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}
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// Predication support.
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bool isPredicated(const MachineInstr *MI) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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// Comparison optimization.
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virtual bool analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const;
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virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
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unsigned SrcReg, unsigned SrcReg2,
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int Mask, int Value,
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const MachineRegisterInfo *MRI) const;
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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};
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}
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#endif
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