mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
643 lines
20 KiB
LLVM
643 lines
20 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512vl --show-mc-encoding| FileCheck %s
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; CHECK-LABEL: test_256_1
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; CHECK: vmovdqu32
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; CHECK: ret
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define <8 x i32> @test_256_1(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x i32>*
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%res = load <8 x i32>, <8 x i32>* %vaddr, align 1
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ret <8 x i32>%res
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}
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; CHECK-LABEL: test_256_2
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test_256_2(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x i32>*
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%res = load <8 x i32>, <8 x i32>* %vaddr, align 32
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ret <8 x i32>%res
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}
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; CHECK-LABEL: test_256_3
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; CHECK: vmovdqa64
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; CHECK: ret
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define void @test_256_3(i8 * %addr, <4 x i64> %data) {
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%vaddr = bitcast i8* %addr to <4 x i64>*
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store <4 x i64>%data, <4 x i64>* %vaddr, align 32
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ret void
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}
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; CHECK-LABEL: test_256_4
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; CHECK: vmovdqu32
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; CHECK: ret
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define void @test_256_4(i8 * %addr, <8 x i32> %data) {
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%vaddr = bitcast i8* %addr to <8 x i32>*
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store <8 x i32>%data, <8 x i32>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_256_5
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; CHECK: vmovdqa32
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; CHECK: ret
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define void @test_256_5(i8 * %addr, <8 x i32> %data) {
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%vaddr = bitcast i8* %addr to <8 x i32>*
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store <8 x i32>%data, <8 x i32>* %vaddr, align 32
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ret void
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}
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; CHECK-LABEL: test_256_6
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; CHECK: vmovdqa64
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; CHECK: ret
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define <4 x i64> @test_256_6(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <4 x i64>*
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%res = load <4 x i64>, <4 x i64>* %vaddr, align 32
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ret <4 x i64>%res
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}
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; CHECK-LABEL: test_256_7
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; CHECK: vmovdqu64
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; CHECK: ret
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define void @test_256_7(i8 * %addr, <4 x i64> %data) {
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%vaddr = bitcast i8* %addr to <4 x i64>*
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store <4 x i64>%data, <4 x i64>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_256_8
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; CHECK: vmovdqu64
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; CHECK: ret
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define <4 x i64> @test_256_8(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <4 x i64>*
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%res = load <4 x i64>, <4 x i64>* %vaddr, align 1
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ret <4 x i64>%res
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}
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; CHECK-LABEL: test_256_9
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; CHECK: vmovapd {{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_256_9(i8 * %addr, <4 x double> %data) {
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%vaddr = bitcast i8* %addr to <4 x double>*
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store <4 x double>%data, <4 x double>* %vaddr, align 32
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ret void
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}
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; CHECK-LABEL: test_256_10
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; CHECK: vmovapd {{.*}} ## encoding: [0x62
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; CHECK: ret
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define <4 x double> @test_256_10(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <4 x double>*
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%res = load <4 x double>, <4 x double>* %vaddr, align 32
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ret <4 x double>%res
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}
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; CHECK-LABEL: test_256_11
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; CHECK: vmovaps {{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_256_11(i8 * %addr, <8 x float> %data) {
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%vaddr = bitcast i8* %addr to <8 x float>*
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store <8 x float>%data, <8 x float>* %vaddr, align 32
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ret void
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}
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; CHECK-LABEL: test_256_12
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; CHECK: vmovaps {{.*}} ## encoding: [0x62
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; CHECK: ret
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define <8 x float> @test_256_12(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x float>*
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%res = load <8 x float>, <8 x float>* %vaddr, align 32
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ret <8 x float>%res
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}
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; CHECK-LABEL: test_256_13
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; CHECK: vmovupd {{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_256_13(i8 * %addr, <4 x double> %data) {
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%vaddr = bitcast i8* %addr to <4 x double>*
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store <4 x double>%data, <4 x double>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_256_14
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; CHECK: vmovupd {{.*}} ## encoding: [0x62
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; CHECK: ret
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define <4 x double> @test_256_14(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <4 x double>*
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%res = load <4 x double>, <4 x double>* %vaddr, align 1
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ret <4 x double>%res
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}
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; CHECK-LABEL: test_256_15
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; CHECK: vmovups {{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_256_15(i8 * %addr, <8 x float> %data) {
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%vaddr = bitcast i8* %addr to <8 x float>*
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store <8 x float>%data, <8 x float>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_256_16
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; CHECK: vmovups {{.*}} ## encoding: [0x62
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; CHECK: ret
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define <8 x float> @test_256_16(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x float>*
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%res = load <8 x float>, <8 x float>* %vaddr, align 1
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ret <8 x float>%res
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}
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; CHECK-LABEL: test_256_17
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; CHECK: vmovdqa32{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x i32> @test_256_17(i8 * %addr, <8 x i32> %old, <8 x i32> %mask1) {
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i32>*
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%r = load <8 x i32>, <8 x i32>* %vaddr, align 32
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%res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> %old
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ret <8 x i32>%res
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}
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; CHECK-LABEL: test_256_18
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; CHECK: vmovdqu32{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x i32> @test_256_18(i8 * %addr, <8 x i32> %old, <8 x i32> %mask1) {
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i32>*
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%r = load <8 x i32>, <8 x i32>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> %old
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ret <8 x i32>%res
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}
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; CHECK-LABEL: test_256_19
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; CHECK: vmovdqa32{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x i32> @test_256_19(i8 * %addr, <8 x i32> %mask1) {
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i32>*
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%r = load <8 x i32>, <8 x i32>* %vaddr, align 32
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%res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> zeroinitializer
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ret <8 x i32>%res
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}
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; CHECK-LABEL: test_256_20
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; CHECK: vmovdqu32{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x i32> @test_256_20(i8 * %addr, <8 x i32> %mask1) {
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i32>*
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%r = load <8 x i32>, <8 x i32>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> zeroinitializer
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ret <8 x i32>%res
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}
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; CHECK-LABEL: test_256_21
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; CHECK: vmovdqa64{{.*{%k[1-7]} }}
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; CHECK: ret
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define <4 x i64> @test_256_21(i8 * %addr, <4 x i64> %old, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x i64>*
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%r = load <4 x i64>, <4 x i64>* %vaddr, align 32
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%res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> %old
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ret <4 x i64>%res
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}
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; CHECK-LABEL: test_256_22
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; CHECK: vmovdqu64{{.*{%k[1-7]} }}
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; CHECK: ret
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define <4 x i64> @test_256_22(i8 * %addr, <4 x i64> %old, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x i64>*
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%r = load <4 x i64>, <4 x i64>* %vaddr, align 1
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%res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> %old
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ret <4 x i64>%res
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}
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; CHECK-LABEL: test_256_23
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; CHECK: vmovdqa64{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <4 x i64> @test_256_23(i8 * %addr, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x i64>*
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%r = load <4 x i64>, <4 x i64>* %vaddr, align 32
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%res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> zeroinitializer
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ret <4 x i64>%res
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}
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; CHECK-LABEL: test_256_24
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; CHECK: vmovdqu64{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <4 x i64> @test_256_24(i8 * %addr, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x i64>*
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%r = load <4 x i64>, <4 x i64>* %vaddr, align 1
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%res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> zeroinitializer
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ret <4 x i64>%res
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}
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; CHECK-LABEL: test_256_25
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; CHECK: vmovaps{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x float> @test_256_25(i8 * %addr, <8 x float> %old, <8 x float> %mask1) {
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%mask = fcmp one <8 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x float>*
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%r = load <8 x float>, <8 x float>* %vaddr, align 32
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%res = select <8 x i1> %mask, <8 x float> %r, <8 x float> %old
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ret <8 x float>%res
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}
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; CHECK-LABEL: test_256_26
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; CHECK: vmovups{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x float> @test_256_26(i8 * %addr, <8 x float> %old, <8 x float> %mask1) {
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%mask = fcmp one <8 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x float>*
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%r = load <8 x float>, <8 x float>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x float> %r, <8 x float> %old
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ret <8 x float>%res
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}
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; CHECK-LABEL: test_256_27
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; CHECK: vmovaps{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x float> @test_256_27(i8 * %addr, <8 x float> %mask1) {
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%mask = fcmp one <8 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x float>*
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%r = load <8 x float>, <8 x float>* %vaddr, align 32
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%res = select <8 x i1> %mask, <8 x float> %r, <8 x float> zeroinitializer
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ret <8 x float>%res
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}
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; CHECK-LABEL: test_256_28
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; CHECK: vmovups{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x float> @test_256_28(i8 * %addr, <8 x float> %mask1) {
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%mask = fcmp one <8 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x float>*
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%r = load <8 x float>, <8 x float>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x float> %r, <8 x float> zeroinitializer
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ret <8 x float>%res
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}
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; CHECK-LABEL: test_256_29
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; CHECK: vmovapd{{.*{%k[1-7]} }}
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; CHECK: ret
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define <4 x double> @test_256_29(i8 * %addr, <4 x double> %old, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x double>*
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%r = load <4 x double>, <4 x double>* %vaddr, align 32
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%res = select <4 x i1> %mask, <4 x double> %r, <4 x double> %old
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ret <4 x double>%res
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}
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; CHECK-LABEL: test_256_30
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; CHECK: vmovupd{{.*{%k[1-7]} }}
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; CHECK: ret
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define <4 x double> @test_256_30(i8 * %addr, <4 x double> %old, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x double>*
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%r = load <4 x double>, <4 x double>* %vaddr, align 1
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%res = select <4 x i1> %mask, <4 x double> %r, <4 x double> %old
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ret <4 x double>%res
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}
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; CHECK-LABEL: test_256_31
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; CHECK: vmovapd{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <4 x double> @test_256_31(i8 * %addr, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x double>*
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%r = load <4 x double>, <4 x double>* %vaddr, align 32
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%res = select <4 x i1> %mask, <4 x double> %r, <4 x double> zeroinitializer
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ret <4 x double>%res
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}
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; CHECK-LABEL: test_256_32
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; CHECK: vmovupd{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <4 x double> @test_256_32(i8 * %addr, <4 x i64> %mask1) {
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%mask = icmp ne <4 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <4 x double>*
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%r = load <4 x double>, <4 x double>* %vaddr, align 1
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%res = select <4 x i1> %mask, <4 x double> %r, <4 x double> zeroinitializer
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ret <4 x double>%res
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}
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; CHECK-LABEL: test_128_1
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; CHECK: vmovdqu32
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; CHECK: ret
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define <4 x i32> @test_128_1(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <4 x i32>*
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%res = load <4 x i32>, <4 x i32>* %vaddr, align 1
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ret <4 x i32>%res
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}
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; CHECK-LABEL: test_128_2
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test_128_2(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <4 x i32>*
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%res = load <4 x i32>, <4 x i32>* %vaddr, align 16
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ret <4 x i32>%res
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}
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; CHECK-LABEL: test_128_3
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; CHECK: vmovdqa64
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; CHECK: ret
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define void @test_128_3(i8 * %addr, <2 x i64> %data) {
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%vaddr = bitcast i8* %addr to <2 x i64>*
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store <2 x i64>%data, <2 x i64>* %vaddr, align 16
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ret void
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}
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; CHECK-LABEL: test_128_4
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; CHECK: vmovdqu32
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; CHECK: ret
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define void @test_128_4(i8 * %addr, <4 x i32> %data) {
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%vaddr = bitcast i8* %addr to <4 x i32>*
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store <4 x i32>%data, <4 x i32>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_128_5
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; CHECK: vmovdqa32
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; CHECK: ret
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define void @test_128_5(i8 * %addr, <4 x i32> %data) {
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%vaddr = bitcast i8* %addr to <4 x i32>*
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store <4 x i32>%data, <4 x i32>* %vaddr, align 16
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ret void
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}
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; CHECK-LABEL: test_128_6
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; CHECK: vmovdqa64
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; CHECK: ret
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define <2 x i64> @test_128_6(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <2 x i64>*
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%res = load <2 x i64>, <2 x i64>* %vaddr, align 16
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ret <2 x i64>%res
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}
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; CHECK-LABEL: test_128_7
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; CHECK: vmovdqu64
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; CHECK: ret
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define void @test_128_7(i8 * %addr, <2 x i64> %data) {
|
|
%vaddr = bitcast i8* %addr to <2 x i64>*
|
|
store <2 x i64>%data, <2 x i64>* %vaddr, align 1
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_8
|
|
; CHECK: vmovdqu64
|
|
; CHECK: ret
|
|
define <2 x i64> @test_128_8(i8 * %addr) {
|
|
%vaddr = bitcast i8* %addr to <2 x i64>*
|
|
%res = load <2 x i64>, <2 x i64>* %vaddr, align 1
|
|
ret <2 x i64>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_9
|
|
; CHECK: vmovapd {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define void @test_128_9(i8 * %addr, <2 x double> %data) {
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
store <2 x double>%data, <2 x double>* %vaddr, align 16
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_10
|
|
; CHECK: vmovapd {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define <2 x double> @test_128_10(i8 * %addr) {
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
%res = load <2 x double>, <2 x double>* %vaddr, align 16
|
|
ret <2 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_11
|
|
; CHECK: vmovaps {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define void @test_128_11(i8 * %addr, <4 x float> %data) {
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
store <4 x float>%data, <4 x float>* %vaddr, align 16
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_12
|
|
; CHECK: vmovaps {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define <4 x float> @test_128_12(i8 * %addr) {
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
%res = load <4 x float>, <4 x float>* %vaddr, align 16
|
|
ret <4 x float>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_13
|
|
; CHECK: vmovupd {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define void @test_128_13(i8 * %addr, <2 x double> %data) {
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
store <2 x double>%data, <2 x double>* %vaddr, align 1
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_14
|
|
; CHECK: vmovupd {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define <2 x double> @test_128_14(i8 * %addr) {
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
%res = load <2 x double>, <2 x double>* %vaddr, align 1
|
|
ret <2 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_15
|
|
; CHECK: vmovups {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define void @test_128_15(i8 * %addr, <4 x float> %data) {
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
store <4 x float>%data, <4 x float>* %vaddr, align 1
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_16
|
|
; CHECK: vmovups {{.*}} ## encoding: [0x62
|
|
; CHECK: ret
|
|
define <4 x float> @test_128_16(i8 * %addr) {
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
%res = load <4 x float>, <4 x float>* %vaddr, align 1
|
|
ret <4 x float>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_17
|
|
; CHECK: vmovdqa32{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <4 x i32> @test_128_17(i8 * %addr, <4 x i32> %old, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x i32>*
|
|
%r = load <4 x i32>, <4 x i32>* %vaddr, align 16
|
|
%res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> %old
|
|
ret <4 x i32>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_18
|
|
; CHECK: vmovdqu32{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <4 x i32> @test_128_18(i8 * %addr, <4 x i32> %old, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x i32>*
|
|
%r = load <4 x i32>, <4 x i32>* %vaddr, align 1
|
|
%res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> %old
|
|
ret <4 x i32>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_19
|
|
; CHECK: vmovdqa32{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <4 x i32> @test_128_19(i8 * %addr, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x i32>*
|
|
%r = load <4 x i32>, <4 x i32>* %vaddr, align 16
|
|
%res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> zeroinitializer
|
|
ret <4 x i32>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_20
|
|
; CHECK: vmovdqu32{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <4 x i32> @test_128_20(i8 * %addr, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x i32>*
|
|
%r = load <4 x i32>, <4 x i32>* %vaddr, align 1
|
|
%res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> zeroinitializer
|
|
ret <4 x i32>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_21
|
|
; CHECK: vmovdqa64{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <2 x i64> @test_128_21(i8 * %addr, <2 x i64> %old, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x i64>*
|
|
%r = load <2 x i64>, <2 x i64>* %vaddr, align 16
|
|
%res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> %old
|
|
ret <2 x i64>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_22
|
|
; CHECK: vmovdqu64{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <2 x i64> @test_128_22(i8 * %addr, <2 x i64> %old, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x i64>*
|
|
%r = load <2 x i64>, <2 x i64>* %vaddr, align 1
|
|
%res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> %old
|
|
ret <2 x i64>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_23
|
|
; CHECK: vmovdqa64{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <2 x i64> @test_128_23(i8 * %addr, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x i64>*
|
|
%r = load <2 x i64>, <2 x i64>* %vaddr, align 16
|
|
%res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> zeroinitializer
|
|
ret <2 x i64>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_24
|
|
; CHECK: vmovdqu64{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <2 x i64> @test_128_24(i8 * %addr, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x i64>*
|
|
%r = load <2 x i64>, <2 x i64>* %vaddr, align 1
|
|
%res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> zeroinitializer
|
|
ret <2 x i64>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_25
|
|
; CHECK: vmovaps{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <4 x float> @test_128_25(i8 * %addr, <4 x float> %old, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
%r = load <4 x float>, <4 x float>* %vaddr, align 16
|
|
%res = select <4 x i1> %mask, <4 x float> %r, <4 x float> %old
|
|
ret <4 x float>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_26
|
|
; CHECK: vmovups{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <4 x float> @test_128_26(i8 * %addr, <4 x float> %old, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
%r = load <4 x float>, <4 x float>* %vaddr, align 1
|
|
%res = select <4 x i1> %mask, <4 x float> %r, <4 x float> %old
|
|
ret <4 x float>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_27
|
|
; CHECK: vmovaps{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <4 x float> @test_128_27(i8 * %addr, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
%r = load <4 x float>, <4 x float>* %vaddr, align 16
|
|
%res = select <4 x i1> %mask, <4 x float> %r, <4 x float> zeroinitializer
|
|
ret <4 x float>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_28
|
|
; CHECK: vmovups{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <4 x float> @test_128_28(i8 * %addr, <4 x i32> %mask1) {
|
|
%mask = icmp ne <4 x i32> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <4 x float>*
|
|
%r = load <4 x float>, <4 x float>* %vaddr, align 1
|
|
%res = select <4 x i1> %mask, <4 x float> %r, <4 x float> zeroinitializer
|
|
ret <4 x float>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_29
|
|
; CHECK: vmovapd{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <2 x double> @test_128_29(i8 * %addr, <2 x double> %old, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
%r = load <2 x double>, <2 x double>* %vaddr, align 16
|
|
%res = select <2 x i1> %mask, <2 x double> %r, <2 x double> %old
|
|
ret <2 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_30
|
|
; CHECK: vmovupd{{.*{%k[1-7]} }}
|
|
; CHECK: ret
|
|
define <2 x double> @test_128_30(i8 * %addr, <2 x double> %old, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
%r = load <2 x double>, <2 x double>* %vaddr, align 1
|
|
%res = select <2 x i1> %mask, <2 x double> %r, <2 x double> %old
|
|
ret <2 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_31
|
|
; CHECK: vmovapd{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <2 x double> @test_128_31(i8 * %addr, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
%r = load <2 x double>, <2 x double>* %vaddr, align 16
|
|
%res = select <2 x i1> %mask, <2 x double> %r, <2 x double> zeroinitializer
|
|
ret <2 x double>%res
|
|
}
|
|
|
|
; CHECK-LABEL: test_128_32
|
|
; CHECK: vmovupd{{.*{%k[1-7]} {z} }}
|
|
; CHECK: ret
|
|
define <2 x double> @test_128_32(i8 * %addr, <2 x i64> %mask1) {
|
|
%mask = icmp ne <2 x i64> %mask1, zeroinitializer
|
|
%vaddr = bitcast i8* %addr to <2 x double>*
|
|
%r = load <2 x double>, <2 x double>* %vaddr, align 1
|
|
%res = select <2 x i1> %mask, <2 x double> %r, <2 x double> zeroinitializer
|
|
ret <2 x double>%res
|
|
}
|
|
|