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shim between the TargetTransformInfo immutable pass and the Subtarget via the TargetMachine and Function. Migrate a single call from BasicTargetTransformInfo as an example and provide shims where TargetMachine begins taking a Function to determine the subtarget. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218004 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
5.3 KiB
C++
160 lines
5.3 KiB
C++
//===-- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// \file
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// This file implements a TargetTransformInfo analysis pass specific to the
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// AMDGPU target machine. It uses the target's detailed information to provide
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// more precise answers to certain TTI queries, while letting the target
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// independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "AMDGPUtti"
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// Declare the pass initialization routine locally as target-specific passes
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// don't have a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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namespace llvm {
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void initializeAMDGPUTTIPass(PassRegistry &);
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}
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namespace {
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class AMDGPUTTI final : public ImmutablePass, public TargetTransformInfo {
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const AMDGPUTargetMachine *TM;
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const AMDGPUSubtarget *ST;
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const AMDGPUTargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
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public:
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AMDGPUTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
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llvm_unreachable("This pass cannot be directly constructed");
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}
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AMDGPUTTI(const AMDGPUTargetMachine *TM)
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: ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
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TLI(TM->getSubtargetImpl()->getTargetLowering()) {
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initializeAMDGPUTTIPass(*PassRegistry::getPassRegistry());
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}
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void initializePass() override { pushTTIStack(this); }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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TargetTransformInfo::getAnalysisUsage(AU);
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}
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/// Pass identification.
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static char ID;
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/// Provide necessary pointer adjustments for the two base classes.
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void *getAdjustedAnalysisPointer(const void *ID) override {
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if (ID == &TargetTransformInfo::ID)
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return (TargetTransformInfo *)this;
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return this;
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}
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bool hasBranchDivergence() const override;
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void getUnrollingPreferences(const Function *F, Loop *L,
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UnrollingPreferences &UP) const override;
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PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const override;
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unsigned getNumberOfRegisters(bool Vector) const override;
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unsigned getRegisterBitWidth(bool Vector) const override;
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unsigned getMaxInterleaveFactor() const override;
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/// @}
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};
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} // end anonymous namespace
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INITIALIZE_AG_PASS(AMDGPUTTI, TargetTransformInfo, "AMDGPUtti",
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"AMDGPU Target Transform Info", true, true, false)
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char AMDGPUTTI::ID = 0;
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ImmutablePass *
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llvm::createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM) {
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return new AMDGPUTTI(TM);
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}
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bool AMDGPUTTI::hasBranchDivergence() const { return true; }
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void AMDGPUTTI::getUnrollingPreferences(const Function *, Loop *L,
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UnrollingPreferences &UP) const {
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UP.Threshold = 300; // Twice the default.
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UP.Count = UINT_MAX;
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UP.Partial = true;
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// TODO: Do we want runtime unrolling?
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for (const BasicBlock *BB : L->getBlocks()) {
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for (const Instruction &I : *BB) {
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const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I);
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if (!GEP || GEP->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
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continue;
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const Value *Ptr = GEP->getPointerOperand();
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const AllocaInst *Alloca = dyn_cast<AllocaInst>(GetUnderlyingObject(Ptr));
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if (Alloca) {
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// We want to do whatever we can to limit the number of alloca
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// instructions that make it through to the code generator. allocas
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// require us to use indirect addressing, which is slow and prone to
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// compiler bugs. If this loop does an address calculation on an
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// alloca ptr, then we want to use a higher than normal loop unroll
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// threshold. This will give SROA a better chance to eliminate these
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// allocas.
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//
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// Don't use the maximum allowed value here as it will make some
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// programs way too big.
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UP.Threshold = 800;
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}
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}
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}
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}
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AMDGPUTTI::PopcntSupportKind
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AMDGPUTTI::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return ST->hasBCNT(TyWidth) ? PSK_FastHardware : PSK_Software;
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}
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unsigned AMDGPUTTI::getNumberOfRegisters(bool Vec) const {
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if (Vec)
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return 0;
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// Number of VGPRs on SI.
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if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
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return 256;
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return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
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}
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unsigned AMDGPUTTI::getRegisterBitWidth(bool) const {
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return 32;
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}
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unsigned AMDGPUTTI::getMaxInterleaveFactor() const {
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// Semi-arbitrary large amount.
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return 64;
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}
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