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https://github.com/c64scene-ar/llvm-6502.git
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6035518e3b
shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
337 lines
12 KiB
C++
337 lines
12 KiB
C++
//===-- R600EmitClauseMarkers.cpp - Emit CF_ALU ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
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/// 128 Alu instructions ; these instructions can access up to 4 prefetched
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/// 4 lines of 16 registers from constant buffers. Such ALU clauses are
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/// initiated by CF_ALU instructions.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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namespace llvm {
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void initializeR600EmitClauseMarkersPass(PassRegistry&);
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}
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namespace {
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class R600EmitClauseMarkers : public MachineFunctionPass {
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private:
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const R600InstrInfo *TII;
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int Address;
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unsigned OccupiedDwords(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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case AMDGPU::DOT_4:
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return 4;
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case AMDGPU::KILL:
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return 0;
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default:
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break;
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}
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// These will be expanded to two ALU instructions in the
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// ExpandSpecialInstructions pass.
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if (TII->isLDSRetInstr(MI->getOpcode()))
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return 2;
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if(TII->isVector(*MI) ||
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TII->isCubeOp(MI->getOpcode()) ||
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TII->isReductionOp(MI->getOpcode()))
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return 4;
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unsigned NumLiteral = 0;
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for (MachineInstr::mop_iterator It = MI->operands_begin(),
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E = MI->operands_end(); It != E; ++It) {
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MachineOperand &MO = *It;
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if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
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++NumLiteral;
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}
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return 1 + NumLiteral;
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}
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bool isALU(const MachineInstr *MI) const {
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if (TII->isALUInstr(MI->getOpcode()))
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return true;
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if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
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return true;
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switch (MI->getOpcode()) {
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case AMDGPU::PRED_X:
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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case AMDGPU::COPY:
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case AMDGPU::DOT_4:
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return true;
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default:
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return false;
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}
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}
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bool IsTrivialInst(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case AMDGPU::KILL:
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case AMDGPU::RETURN:
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case AMDGPU::IMPLICIT_DEF:
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return true;
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default:
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return false;
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}
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}
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std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
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// Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
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// (See also R600ISelLowering.cpp)
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// ConstIndex value is in [0, 4095];
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return std::pair<unsigned, unsigned>(
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((Sel >> 2) - 512) >> 12, // KC_BANK
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// Line Number of ConstIndex
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// A line contains 16 constant registers however KCX bank can lock
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// two line at the same time ; thus we want to get an even line number.
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// Line number can be retrieved with (>>4), using (>>5) <<1 generates
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// an even number.
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((((Sel >> 2) - 512) & 4095) >> 5) << 1);
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}
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bool SubstituteKCacheBank(MachineInstr *MI,
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std::vector<std::pair<unsigned, unsigned> > &CachedConsts,
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bool UpdateInstr = true) const {
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std::vector<std::pair<unsigned, unsigned> > UsedKCache;
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if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4)
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return true;
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const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Consts =
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TII->getSrcs(MI);
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assert((TII->isALUInstr(MI->getOpcode()) ||
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MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const");
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for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
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if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
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continue;
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unsigned Sel = Consts[i].second;
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unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
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unsigned KCacheIndex = Index * 4 + Chan;
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const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
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if (CachedConsts.empty()) {
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CachedConsts.push_back(BankLine);
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UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
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continue;
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}
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if (CachedConsts[0] == BankLine) {
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UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
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continue;
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}
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if (CachedConsts.size() == 1) {
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CachedConsts.push_back(BankLine);
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UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
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continue;
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}
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if (CachedConsts[1] == BankLine) {
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UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
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continue;
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}
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return false;
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}
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if (!UpdateInstr)
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return true;
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for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
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if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
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continue;
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switch(UsedKCache[j].first) {
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case 0:
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Consts[i].first->setReg(
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AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
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break;
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case 1:
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Consts[i].first->setReg(
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AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
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break;
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default:
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llvm_unreachable("Wrong Cache Line");
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}
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j++;
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}
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return true;
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}
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bool canClauseLocalKillFitInClause(
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unsigned AluInstCount,
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std::vector<std::pair<unsigned, unsigned> > KCacheBanks,
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MachineBasicBlock::iterator Def,
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MachineBasicBlock::iterator BBEnd) {
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const R600RegisterInfo &TRI = TII->getRegisterInfo();
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for (MachineInstr::const_mop_iterator
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MOI = Def->operands_begin(),
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MOE = Def->operands_end(); MOI != MOE; ++MOI) {
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if (!MOI->isReg() || !MOI->isDef() ||
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TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
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continue;
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// Def defines a clause local register, so check that its use will fit
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// in the clause.
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unsigned LastUseCount = 0;
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for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) {
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AluInstCount += OccupiedDwords(UseI);
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// Make sure we won't need to end the clause due to KCache limitations.
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if (!SubstituteKCacheBank(UseI, KCacheBanks, false))
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return false;
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// We have reached the maximum instruction limit before finding the
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// use that kills this register, so we cannot use this def in the
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// current clause.
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if (AluInstCount >= TII->getMaxAlusPerClause())
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return false;
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// Register kill flags have been cleared by the time we get to this
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// pass, but it is safe to assume that all uses of this register
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// occur in the same basic block as its definition, because
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// it is illegal for the scheduler to schedule them in
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// different blocks.
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if (UseI->findRegisterUseOperandIdx(MOI->getReg()))
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LastUseCount = AluInstCount;
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if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1)
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break;
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}
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if (LastUseCount)
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return LastUseCount <= TII->getMaxAlusPerClause();
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llvm_unreachable("Clause local register live at end of clause.");
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}
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return true;
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}
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MachineBasicBlock::iterator
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MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) {
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MachineBasicBlock::iterator ClauseHead = I;
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std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
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bool PushBeforeModifier = false;
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unsigned AluInstCount = 0;
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for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
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if (IsTrivialInst(I))
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continue;
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if (!isALU(I))
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break;
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if (AluInstCount > TII->getMaxAlusPerClause())
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break;
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if (I->getOpcode() == AMDGPU::PRED_X) {
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// We put PRED_X in its own clause to ensure that ifcvt won't create
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// clauses with more than 128 insts.
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// IfCvt is indeed checking that "then" and "else" branches of an if
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// statement have less than ~60 insts thus converted clauses can't be
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// bigger than ~121 insts (predicate setter needs to be in the same
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// clause as predicated alus).
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if (AluInstCount > 0)
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break;
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if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
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PushBeforeModifier = true;
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AluInstCount ++;
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continue;
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}
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// XXX: GROUP_BARRIER instructions cannot be in the same ALU clause as:
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//
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// * KILL or INTERP instructions
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// * Any instruction that sets UPDATE_EXEC_MASK or UPDATE_PRED bits
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// * Uses waterfalling (i.e. INDEX_MODE = AR.X)
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//
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// XXX: These checks have not been implemented yet.
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if (TII->mustBeLastInClause(I->getOpcode())) {
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I++;
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break;
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}
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// If this instruction defines a clause local register, make sure
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// its use can fit in this clause.
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if (!canClauseLocalKillFitInClause(AluInstCount, KCacheBanks, I, E))
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break;
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if (!SubstituteKCacheBank(I, KCacheBanks))
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break;
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AluInstCount += OccupiedDwords(I);
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}
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unsigned Opcode = PushBeforeModifier ?
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AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
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BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
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// We don't use the ADDR field until R600ControlFlowFinalizer pass, where
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// it is safe to assume it is 0. However if we always put 0 here, the ifcvt
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// pass may assume that identical ALU clause starter at the beginning of a
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// true and false branch can be factorized which is not the case.
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.addImm(Address++) // ADDR
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.addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
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.addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
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.addImm(KCacheBanks.empty()?0:2) // KM0
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.addImm((KCacheBanks.size() < 2)?0:2) // KM1
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.addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
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.addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
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.addImm(AluInstCount) // COUNT
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.addImm(1); // Enabled
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return I;
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}
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public:
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static char ID;
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R600EmitClauseMarkers() : MachineFunctionPass(ID), TII(nullptr), Address(0) {
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initializeR600EmitClauseMarkersPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo());
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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MachineBasicBlock::iterator I = MBB.begin();
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if (I->getOpcode() == AMDGPU::CF_ALU)
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continue; // BB was already parsed
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for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
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if (isALU(I))
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I = MakeALUClause(MBB, I);
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else
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++I;
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}
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}
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return false;
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}
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const char *getPassName() const override {
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return "R600 Emit Clause Markers Pass";
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}
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};
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char R600EmitClauseMarkers::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(R600EmitClauseMarkers, "emitclausemarkers",
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"R600 Emit Clause Markters", false, false)
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INITIALIZE_PASS_END(R600EmitClauseMarkers, "emitclausemarkers",
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"R600 Emit Clause Markters", false, false)
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llvm::FunctionPass *llvm::createR600EmitClauseMarkers() {
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return new R600EmitClauseMarkers();
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}
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