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https://github.com/c64scene-ar/llvm-6502.git
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Summary: Hi Eric, this patch cleans up the layering violation that you're fixing across backends. Anything else I need to fix on bpf backend side? Thanks Reviewers: echristo Reviewed By: echristo Differential Revision: http://reviews.llvm.org/D7355 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227865 91177308-0d34-0410-b5e6-96231b3b80d8
642 lines
21 KiB
C++
642 lines
21 KiB
C++
//===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that BPF uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "BPFISelLowering.h"
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#include "BPF.h"
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#include "BPFTargetMachine.h"
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#include "BPFSubtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/DiagnosticPrinter.h"
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using namespace llvm;
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#define DEBUG_TYPE "bpf-lower"
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namespace {
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// Diagnostic information for unimplemented or unsupported feature reporting.
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class DiagnosticInfoUnsupported : public DiagnosticInfo {
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private:
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// Debug location where this diagnostic is triggered.
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DebugLoc DLoc;
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const Twine &Description;
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const Function &Fn;
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SDValue Value;
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static int KindID;
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static int getKindID() {
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if (KindID == 0)
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KindID = llvm::getNextAvailablePluginDiagnosticKind();
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return KindID;
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}
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public:
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DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
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SDValue Value)
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: DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
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Description(Desc), Fn(Fn), Value(Value) {}
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void print(DiagnosticPrinter &DP) const override {
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std::string Str;
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raw_string_ostream OS(Str);
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if (DLoc.isUnknown() == false) {
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DILocation DIL(DLoc.getAsMDNode(Fn.getContext()));
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StringRef Filename = DIL.getFilename();
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unsigned Line = DIL.getLineNumber();
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unsigned Column = DIL.getColumnNumber();
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OS << Filename << ':' << Line << ':' << Column << ' ';
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}
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OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
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<< Description;
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if (Value)
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Value->print(OS);
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OS << '\n';
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OS.flush();
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DP << Str;
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}
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static bool classof(const DiagnosticInfo *DI) {
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return DI->getKind() == getKindID();
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}
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};
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int DiagnosticInfoUnsupported::KindID = 0;
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}
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BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i64, &BPF::GPRRegClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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setStackPointerRegisterToSaveRestore(BPF::R11);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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setOperationAction(ISD::MULHU, MVT::i64, Expand);
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setOperationAction(ISD::MULHS, MVT::i64, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::ADDC, MVT::i64, Expand);
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setOperationAction(ISD::ADDE, MVT::i64, Expand);
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setOperationAction(ISD::SUBC, MVT::i64, Expand);
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setOperationAction(ISD::SUBE, MVT::i64, Expand);
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// no UNDEF allowed
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setOperationAction(ISD::UNDEF, MVT::i64, Expand);
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setOperationAction(ISD::ROTR, MVT::i64, Expand);
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setOperationAction(ISD::ROTL, MVT::i64, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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setOperationAction(ISD::CTTZ, MVT::i64, Custom);
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setOperationAction(ISD::CTLZ, MVT::i64, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
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setOperationAction(ISD::CTPOP, MVT::i64, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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// Extended load operations for i1 types must be promoted
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
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}
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setBooleanContents(ZeroOrOneBooleanContent);
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// Function alignments (log2)
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setMinFunctionAlignment(3);
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setPrefFunctionAlignment(3);
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// inline memcpy() for kernel to see explicit copy
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MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128;
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MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128;
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MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128;
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}
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SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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case ISD::BR_CC:
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return LowerBR_CC(Op, DAG);
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::SELECT_CC:
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return LowerSELECT_CC(Op, DAG);
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default:
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llvm_unreachable("unimplemented operand");
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}
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}
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// Calling Convention Implementation
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#include "BPFGenCallingConv.inc"
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SDValue BPFTargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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break;
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}
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
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for (auto &VA : ArgLocs) {
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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EVT RegVT = VA.getLocVT();
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switch (RegVT.getSimpleVT().SimpleTy) {
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default: {
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errs() << "LowerFormalArguments Unhandled argument type: "
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<< RegVT.getSimpleVT().SimpleTy << '\n';
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llvm_unreachable(0);
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}
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case MVT::i64:
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unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
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// If this is an 8/16/32-bit value, it is really passed promoted to 64
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
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InVals.push_back(ArgValue);
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}
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} else {
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DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
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"defined with too many args", SDValue());
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DAG.getContext()->diagnose(Err);
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}
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}
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if (IsVarArg || MF.getFunction()->hasStructRetAttr()) {
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DiagnosticInfoUnsupported Err(
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DL, *MF.getFunction(),
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"functions with VarArgs or StructRet are not supported", SDValue());
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DAG.getContext()->diagnose(Err);
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}
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return Chain;
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}
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SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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auto &Outs = CLI.Outs;
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auto &OutVals = CLI.OutVals;
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auto &Ins = CLI.Ins;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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bool &IsTailCall = CLI.IsTailCall;
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CallingConv::ID CallConv = CLI.CallConv;
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bool IsVarArg = CLI.IsVarArg;
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MachineFunction &MF = DAG.getMachineFunction();
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// BPF target does not support tail call optimization.
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IsTailCall = false;
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switch (CallConv) {
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default:
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report_fatal_error("Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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break;
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}
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
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unsigned NumBytes = CCInfo.getNextStackOffset();
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if (Outs.size() >= 6) {
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DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
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"too many args to ", Callee);
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DAG.getContext()->diagnose(Err);
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}
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for (auto &Arg : Outs) {
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ISD::ArgFlagsTy Flags = Arg.Flags;
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if (!Flags.isByVal())
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continue;
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DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
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"pass by value not supported ", Callee);
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DAG.getContext()->diagnose(Err);
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}
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Chain = DAG.getCALLSEQ_START(
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Chain, DAG.getConstant(NumBytes, getPointerTy(), true), CLI.DL);
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SmallVector<std::pair<unsigned, SDValue>, 5> RegsToPass;
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// Walk arg assignments
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = OutVals[i];
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown loc info");
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case CCValAssign::Full:
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break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
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break;
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}
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// Push arguments into RegsToPass vector
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if (VA.isRegLoc())
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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else
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llvm_unreachable("call arg pass bug");
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}
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SDValue InFlag;
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// Build a sequence of copy-to-reg nodes chained together with token chain and
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// flag operands which copy the outgoing args into registers. The InFlag in
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// necessary since all emitted instructions must be stuck together.
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for (auto &Reg : RegsToPass) {
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Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, getPointerTy(),
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G->getOffset(), 0);
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), 0);
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (auto &Reg : RegsToPass)
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Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
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if (InFlag.getNode())
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Ops.push_back(InFlag);
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Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
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InFlag = Chain.getValue(1);
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// Create the CALLSEQ_END node.
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Chain = DAG.getCALLSEQ_END(
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Chain, DAG.getConstant(NumBytes, getPointerTy(), true),
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DAG.getConstant(0, getPointerTy(), true), InFlag, CLI.DL);
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
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InVals);
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}
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SDValue
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BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const {
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// CCValAssign - represent the assignment of the return value to a location
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SmallVector<CCValAssign, 16> RVLocs;
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MachineFunction &MF = DAG.getMachineFunction();
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
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if (MF.getFunction()->getReturnType()->isAggregateType()) {
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DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
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"only integer returns supported", SDValue());
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DAG.getContext()->diagnose(Err);
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}
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad.
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Flag = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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}
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unsigned Opc = BPFISD::RET_FLAG;
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RetOps[0] = Chain; // Update chain.
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// Add the flag if we have it.
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if (Flag.getNode())
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RetOps.push_back(Flag);
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return DAG.getNode(Opc, DL, MVT::Other, RetOps);
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}
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SDValue BPFTargetLowering::LowerCallResult(
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SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
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if (Ins.size() >= 2) {
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DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
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"only small returns supported", SDValue());
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DAG.getContext()->diagnose(Err);
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}
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CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
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// Copy all of the result registers out of their specified physreg.
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for (auto &Val : RVLocs) {
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Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
|
|
Val.getValVT(), InFlag).getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
InVals.push_back(Chain.getValue(0));
|
|
}
|
|
|
|
return Chain;
|
|
}
|
|
|
|
static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
|
|
switch (CC) {
|
|
default:
|
|
break;
|
|
case ISD::SETULT:
|
|
case ISD::SETULE:
|
|
case ISD::SETLT:
|
|
case ISD::SETLE:
|
|
CC = ISD::getSetCCSwappedOperands(CC);
|
|
std::swap(LHS, RHS);
|
|
break;
|
|
}
|
|
}
|
|
|
|
SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDValue LHS = Op.getOperand(2);
|
|
SDValue RHS = Op.getOperand(3);
|
|
SDValue Dest = Op.getOperand(4);
|
|
SDLoc DL(Op);
|
|
|
|
NegateCC(LHS, RHS, CC);
|
|
|
|
return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
|
|
DAG.getConstant(CC, MVT::i64), Dest);
|
|
}
|
|
|
|
SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
SDValue TrueV = Op.getOperand(2);
|
|
SDValue FalseV = Op.getOperand(3);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
SDLoc DL(Op);
|
|
|
|
NegateCC(LHS, RHS, CC);
|
|
|
|
SDValue TargetCC = DAG.getConstant(CC, MVT::i64);
|
|
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
|
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
|
|
|
|
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
|
|
}
|
|
|
|
const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
default:
|
|
return NULL;
|
|
case BPFISD::RET_FLAG:
|
|
return "BPFISD::RET_FLAG";
|
|
case BPFISD::CALL:
|
|
return "BPFISD::CALL";
|
|
case BPFISD::SELECT_CC:
|
|
return "BPFISD::SELECT_CC";
|
|
case BPFISD::BR_CC:
|
|
return "BPFISD::BR_CC";
|
|
case BPFISD::Wrapper:
|
|
return "BPFISD::Wrapper";
|
|
}
|
|
}
|
|
|
|
SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
|
|
|
|
return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB) const {
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
|
|
assert(Opc == BPF::Select && "Unexpected instr type to insert");
|
|
|
|
// To "insert" a SELECT instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator I = BB;
|
|
++I;
|
|
|
|
// ThisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// jmp_XX r1, r2 goto Copy1MBB
|
|
// fallthrough --> Copy0MBB
|
|
MachineBasicBlock *ThisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
F->insert(I, Copy0MBB);
|
|
F->insert(I, Copy1MBB);
|
|
// Update machine-CFG edges by transferring all successors of the current
|
|
// block to the new block which will contain the Phi node for the select.
|
|
Copy1MBB->splice(Copy1MBB->begin(), BB,
|
|
std::next(MachineBasicBlock::iterator(MI)), BB->end());
|
|
Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(Copy0MBB);
|
|
BB->addSuccessor(Copy1MBB);
|
|
|
|
// Insert Branch if Flag
|
|
unsigned LHS = MI->getOperand(1).getReg();
|
|
unsigned RHS = MI->getOperand(2).getReg();
|
|
int CC = MI->getOperand(3).getImm();
|
|
switch (CC) {
|
|
case ISD::SETGT:
|
|
BuildMI(BB, DL, TII.get(BPF::JSGT_rr))
|
|
.addReg(LHS)
|
|
.addReg(RHS)
|
|
.addMBB(Copy1MBB);
|
|
break;
|
|
case ISD::SETUGT:
|
|
BuildMI(BB, DL, TII.get(BPF::JUGT_rr))
|
|
.addReg(LHS)
|
|
.addReg(RHS)
|
|
.addMBB(Copy1MBB);
|
|
break;
|
|
case ISD::SETGE:
|
|
BuildMI(BB, DL, TII.get(BPF::JSGE_rr))
|
|
.addReg(LHS)
|
|
.addReg(RHS)
|
|
.addMBB(Copy1MBB);
|
|
break;
|
|
case ISD::SETUGE:
|
|
BuildMI(BB, DL, TII.get(BPF::JUGE_rr))
|
|
.addReg(LHS)
|
|
.addReg(RHS)
|
|
.addMBB(Copy1MBB);
|
|
break;
|
|
case ISD::SETEQ:
|
|
BuildMI(BB, DL, TII.get(BPF::JEQ_rr))
|
|
.addReg(LHS)
|
|
.addReg(RHS)
|
|
.addMBB(Copy1MBB);
|
|
break;
|
|
case ISD::SETNE:
|
|
BuildMI(BB, DL, TII.get(BPF::JNE_rr))
|
|
.addReg(LHS)
|
|
.addReg(RHS)
|
|
.addMBB(Copy1MBB);
|
|
break;
|
|
default:
|
|
report_fatal_error("unimplemented select CondCode " + Twine(CC));
|
|
}
|
|
|
|
// Copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to Copy1MBB
|
|
BB = Copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(Copy1MBB);
|
|
|
|
// Copy1MBB:
|
|
// %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
|
|
// ...
|
|
BB = Copy1MBB;
|
|
BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(5).getReg())
|
|
.addMBB(Copy0MBB)
|
|
.addReg(MI->getOperand(4).getReg())
|
|
.addMBB(ThisMBB);
|
|
|
|
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|